STG4158BJR

STG4158 Low-voltage 0.6 Ω typ. single SPDT switch with break-before-make feature and 15 kV ESD protection Datasheet − production data Features ■ Power-off and overvoltage protection ■ Wide operating voltage range: VCC (opr) = 1.65 to 4.5 V ■ Low ON-resistance VIN = 0 V: – RON = 0.85 Ω (max.) at VCC = 4.5 V Flip Chip6 ■ Latch-up performance exceeds 300 mA JESD 17 ■ ESD performance tested on (D pin) – 8 kV IEC-61000-4-2 ESD, contact discharge – 15 kV IEC-61000-4-2 ESD, air discharge ■ ESD performance test on all other pins – 3 kV human body model – 200 V machine model (IEC61340-3-2 level M2) – 1000 V charge device model (JESD22 C101) Wafer 7AFER Description The STG4158 is a high-speed CMOS low-voltage single analog SPDT (single-pole dual throw) switch or 2:1 multiplexer/demultiplexer switch fabricated in silicon gate C2MOS technology. Designed to operate from 1.65 to 4.5 V, this device is ideal for portable applications. It offers low ON-resistance (0.6 Ω) at VCC = 4.5 V (typical TA = 25 °C). The SEL input threshold is compatible with 1.8 V, and provides control to the switches. Table 1. The switch S1 is ON (connected to common port D) when the SEL input is held high and OFF (high-impedance state exists between the two ports) when SEL is held low. The switch S2 is ON (connected to common port D) when the SEL input is held low and OFF (high-impedance state exists between the two ports) when SEL is held high. The SEL input has an integrated weak pull-down resistor to prevent the SEL signal from floating. For low-power consumption, the SEL input must be grounded. The STG4158 features power-off and overvoltage protection, enabling the device to be isolated during voltage fault events. Device summary Order code Package Packing STG4158BJR Flip Chip6 Tape and reel JSTG4158-CD1 April 2012 This is information on a product in full production. Unsawn wafer Doc ID 14140 Rev 2 1/24 www.st.com 1 Contents STG4158 Contents 1 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Die description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 Doc ID 14140 Rev 2 STG4158 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤ 5 ns) . . Analog switch characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C) . . Voltage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip Chip6 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Doc ID 14140 Rev 2 ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....1 .....5 .....6 .....7 .....7 .....8 . . . . 10 . . . . 11 . . . . 12 . . . . 18 . . . . 22 . . . . 23 3/24 List of figures STG4158 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. 4/24 Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (bump side view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Voltage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ON-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OFF leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Channel-to-channel crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OFF isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Break-before-make time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Switching time and charge injection (VGEN = 0 V, R GEN = 0 Ω, RL = 1 MΩ, CL = 100 pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Turn-ON, turn-OFF delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flip Chip6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flip Chip6 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flip Chip6 tape specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Flip Chip6 reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTS4158-CD1 die plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 14140 Rev 2 STG4158 1 Logic diagram Logic diagram Figure 1. Functional diagram S1 D S2 SEL Figure 2. Input equivalent circuit $ 3 3 3%, 2 3%, #36 Table 2. Truth table SEL Switch S1 Switch S2 H ON OFF(1) L OFF(1) ON 1. High impedance. Doc ID 14140 Rev 2 5/24 Logic diagram 6/24 STG4158 Figure 3. Pin connection (bump side view) Table 3. Pin description Flip Chip Symbol 1, 3 S1, S2 5 D 6 SEL Control 4 VCC Positive supply voltage 2 GND Ground (0 V) Doc ID 14140 Rev 2 Name and function Independent channels Common channel STG4158 2 Maximum rating Maximum rating Stressing the device above the ratings listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 5: Recommended operating conditions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol VCC Parameter Supply voltage Unit -0.5 to 5.5 V -0.5 to VCC + 0.5 V -0.5 to 5.5 V -0.5 to VCC + 0.5 V VI DC input voltage VIC DC control input voltage VO DC output voltage IIKC DC input diode current on control pin (VSEL < 0 V) - 50 mA IIK DC input diode current (VSEL < 0 V) ± 50 mA IOK DC output diode current ± 20 mA IO DC output current ± 300 mA IOP DC output current peak (pulse at 1 ms, 10% duty cycle) ± 500 mA ± 100 mA 500 mW -65 to 150 °C 260 °C Value Unit 1.65 to 4.5 V ICC or IGND DC VCC or ground current 1. Value PD Power dissipation at TA = 70 Tstg Storage temperature TL Lead temperature (10 sec.) °C(1) Derate above 70 °C by 18.5 mW/°C. Table 5. Recommended operating conditions Symbol VCC Parameter Supply voltage VI Input voltage 0 to VCC V VIC Control input voltage 0 to VCC V VO Output voltage 0 to VCC V Top Operating temperature -40 to 85 °C dt/dv Input rise and fall time control input VCC = 1.65 to 2.7 V 0 to 20 VCC = 3.0 to 4.5 V 0 to 10 Doc ID 14140 Rev 2 ns/V 7/24 Electrical characteristics 3 STG4158 Electrical characteristics Table 6. DC specifications Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min. VIH VIL High-level input voltage Low-level input voltage RON ΔRON RFLAT 8/24 ONresistance match between channels ONresistance flatness RSEL SEL pulldown resistance IOFF Sn OFF state leakage current ION Sn ON state leakage current Max. Min. 1.65 – 1.95 0.9 0.9 2.25 – 2.7 0.9 0.9 3.0 – 4.3 1.0 1.0 4.5 1.1 1.1 Max. V 1.65 – 1.95 0.6 0.6 2.25 – 2.7 0.6 0.6 3.0 – 4.3 0.7 0.7 4.5 0.7 0.7 V 2.0 3.0 0.9 1.3 3.7 – 4.5 0.6 0.85 1.65 – 2.20 40 400 10 100 10 100 1.65 – 2.20 ONresistance Typ. -40 to 85 °C Unit 2.25 – 3.6 2.25 – 3.6 VS = 0 V to VCC IS = 100 mA VS = 0 V to VCC IS = 100 mA 3.7 – 4.5 mΩ 1.2 1.65 – 2.20 2.25 – 3.6 Ω VS = 0 V to VCC IS = 100 mA 0.3 0.6 3.7 – 4.5 0.2 0.4 1.65 – 4.5 5000 Ω kΩ 1.65 – 4.5 VS = 0, VD = VCC VS = VCC, VD = 0 -30 30 -300 300 nA 1.65 – 4.5 VS = 0 to VCC VD = open -20 20 -200 200 nA Doc ID 14140 Rev 2 STG4158 Electrical characteristics Table 6. DC specifications (continued) Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min. 1.65 – 4.5 ID IS D ON state leakage current S ON state leakage current ICC ISEL ICCLV SEL leakage current Quiescent supply current lowvoltage driving -30 Max. Min. Max. 30 -300 300 nA Floating VD = 0 - 4.5 10 25 μA 0 – 0.5 VD = 0 - 4.5 10 25 μA VCC > 0.5 VD > VCC + 0.4 10 25 μA 1.65 – 4.5 VS = 0 to VCC VD = open 300 nA -30 30 -300 Floating VS = 0 - 4.5 5 15 μA 0 – 0.5 VS = 0 - 4.5 5 15 μA VS > VCC + 0.4 5 15 μA 5.6 10 μA 9 20 μA VCC > 0.5 Quiescent supply current VS = open VD = 0 to VCC Typ. -40 to 85 °C Unit 2.5 4.5 VSEL = VCC 1.65 – 4.5 VSEL = GND 0.05 0.1 μA 1.65 – 4.5 VSEL = GND 0.1 1.0 μA 2.5 VSEL = VCC 0.5 1.0 μA 4.5 VSEL = VCC 1.0 2.0 μA 4.5 VSEL = 1.45 V 8 20 μA Doc ID 14140 Rev 2 9/24 Electrical characteristics Table 7. STG4158 AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤ 5 ns) Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min. tPLH, tPHL Propagation delay 1.65 – 1.95 0.13 2.25 – 2.7 0.15 3.0 – 3.6 0.16 3.7 – 4.5 0.16 2.25 – 2.7 Turn-on time 3.0 – 3.6 VS = VCC RL = 50 Ω CL = 30 pF 1.65 – 1.95 2.25 – 2.7 Turn-off time 3.0 – 3.6 VS = VCC RL = 50 Ω CL = 30 pF 1.65 – 1.95 Break-beforemake time delay 2.25 – 2.7 3.0 – 3.6 CL = 35 pF RL = 50 Ω VS = VCC/2 3.7 – 4.5 1.65 – 1.95 Q Charge injection 2.25 – 2.7 3.0 – 3.6 112 160 64 86 43 58 28 38 14 20 13 18 13 18 13 18 10 86 10 56 5 31 5 25 ns 70 CL = 1 nF VGEN = 0 V 3.7 – -4.5 10/24 Max. ns 3.7 – 4.5 tD Min. ns 3.7 – 4.5 tOFF Max. ns 1.65 – 1.95 tON Typ. -40 to 85 °C Unit Doc ID 14140 Rev 2 140 pC 190 230 STG4158 Electrical characteristics Analog switch characteristics (CL = 5 pF, RL = 50 Ω, TA = 25 °C) Table 8. Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min. OIRR Xtalk 1. OFF-isolation (1) Crosstalk 1.65 – 4.5 1.65 – 4.5 Typ. Max. -40 to 85 °C Min. Unit Max. VS = 1 VRMS f = 100 kHz -76 VS = 1 VRMS f = 1 MHz -55 VS = 1 VRMS f = 5 MHz -40 VS = 1 VRMS f = 100 kHz -81 VS = 1 VRMS f = 1 MHz -61 VS = 1 VRMS f = 5 MHz -48 0.015 % MHz THD Total harmonic distortion 2.3 – 4.5 RL = 600 Ω CL = 50 pF VS = VCC VPP f = 600 Hz to 20 kHz BW -3 dB bandwidth (switch ON) 1.65 – 4.5 RL = 50 Ω 40 CSEL Control pin input capacitance 1.8 – 4.5 VL = VCC 30 CSn Sn port capacitance 1.8 – 4.5 VL = VCC 80 CD D port capacitance when switch is enabled 1.8 – 4.5 VL = VCC 190 dB dB pF OFF-isolation = 20 log10 (V D/VS), VD = output, VS = input to OFF switch. Doc ID 14140 Rev 2 11/24 Application information 4 STG4158 Application information Power-off and overvoltage protection The STG4158 has two operation modes: 1. Normal operation mode 2. Isolation mode In normal operation mode, the switch functions as a normal SPDT, with the SEL pin that selects the switch to be either ON or OFF. Either S1 or S2 is connected to common channel D. In isolation mode, all the switches are OFF. S1 or S2 are isolated from common channel D. The S1, S2, D ports have a 1 MΩ impedance to ground. The operation modes are made possible by special detection circuitry that detects the voltage level at D, S1 and S2 supplies. Depending on these voltage levels, the device goes into isolation mode or normal operation mode accordingly. Isolation mode is a feature of the device that is useful during fault conditions that occur in the application environment. Table 9. Voltage conditions VCC VD,S (voltage at common port D, S1 or S2) Floating 0 – 4.5 V All switches OFF - S1, S2 and D are isolated from each other. Isolation 0 – 0.5 V 0 – 4.5 V All switches OFF - S1, S2 and D are isolated from each other. Isolation VCC > 0.5 VD, S > VCC + 0.4 All switches OFF - S1, S2 and D are isolated from each other. Isolation 1.65 – 4.5 V 0 – V CC Either S1 or S2 is connected to D, depending on SEL input. Normal Figure 4. Voltage condition Mode Voltage conditions The SEL input has an integrated weak pull-down resistor RSEL to prevent the SEL signal from floating. For lower power consumption, the SEL input must be grounded. 12/24 Doc ID 14140 Rev 2 STG4158 5 Test circuits Test circuits Figure 5. ON-resistance )$3 6 6## $ 3 63 3 ). '.$ '.$ #36 Figure 6. Bandwidth 6## $ 3 6/54 3 63 6 ## ). '.$ #36 Doc ID 14140 Rev 2 13/24 Test circuits STG4158 Figure 7. OFF leakage 6## )3/&& $ )$/&& ! ! 633 6$ 3 6## ). '.$ #36 Figure 8. Channel-to-channel crosstalk 6## 6/54 $ 3 3 63 6## ). '.$ #36 14/24 Doc ID 14140 Rev 2 STG4158 Test circuits Figure 9. OFF isolation 6## 3 6/54 3 '.$ ). 63 '.$ #36 Figure 10. Test circuit 6## 05,3% '%.%2!4/2 $54 24 #, 2, 3#6 1. CL = 5/35 pF or equivalent: (includes jig capacitance). 2. RL = 50 Ω or equivalent. 3. RT = ZOUT of pulse generator (typically 50 Ω). Doc ID 14140 Rev 2 15/24 Test circuits STG4158 Figure 11. Break-before-make time delay 6## $ 3 63 6/54 2, #, 3 ). 6). '.$ #3V Figure 12. Switching time and charge injection (VGEN = 0 V, RGEN = 0 Ω, RL = 1 MΩ, CL = 100 pF) 6## 2'%. 6## $ 3 6'%. 6/54 2, 6).   #, '.$ 3 T/.  ). T/&&  6/54 6). '.$ #36 #3V Figure 13. Turn-ON, turn-OFF delay time 6## 6## 3 $ 6/54 6).  '.$ 2, #, T/&& 3  ). 6). '.$ T/. #36 16/24  6/54 Doc ID 14140 Rev 2 #36 STG4158 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14. Flip Chip6 package outline 1. The terminal pin 1 on the bumps side is identified by a distinguishing feature (for instance by a circular “clear area” - typically 0.1 mm diameter). The terminal pin 1 on the backside of the product is identified by a distinguishing feature (for instance by a circular “dot” - typically 0.5 mm diameter). 2. Drawing not to scale. Doc ID 14140 Rev 2 17/24 Package mechanical data Table 10. STG4158 Flip Chip6 mechanical data Dimensions (mm.) Symbol Min. Typ. Max. A 0.545 0.6 0.655 A1 0.17 0.2 0.23 A2 0.375 0.4 0.425 b 0.23 0.255 0.28 D 0.813 0.828 0.843 D1 0.39 0.4 0.41 E 1.213 1.228 1.243 E1 0.79 0.8 0.81 e 0.36 0.4 0.44 f 0.204 0.214 0.224 ccc 0.05 Figure 15. Footprint recommendation 0.80 0.40 0.40 B A 1 Grid placement area Figure 16. Flip Chip6 marking 158 18/24 Doc ID 14140 Rev 2 2 3 0.22 STG4158 Package mechanical data Figure 17. Flip Chip6 tape specification 1. All dimensions in mm. Doc ID 14140 Rev 2 19/24 Package mechanical data STG4158 Figure 18. Flip Chip6 reel information 1. Material properties: 1) Antistatic (white or blue). 2) Conductive (black). 20/24 Doc ID 14140 Rev 2 STG4158 7 Die description Die description Product JSTG4158-CD1 ● Wafer size: 203 mm (8 inches) ● Wafer thickness: 725 μm + 20 μm ● Die identification: UP98A. Die layout ● Design die size (X x Y): 1128 x 728 μm ● Scribe line: 100 x 100 μm ● Stepping die size: 1228 x 828 μm ● Pad opening: 184 x 184 μm ● DI: die identification (at the position shown in Figure 19) ● Pads: pad contact (at the position shown in Figure 19 and Table 11). Figure 19. JSTG4158-CD1 die plot Refer to Table 11 for the pad locations. Doc ID 14140 Rev 2 21/24 Die description STG4158 Table 11. Pad information Pad function X (μm) Y(μm) S1 -400 200 GND 0 200 S2 400 200 VCC 400 -200 D 0 -200 SEL -400 -200 Pad locations are measured relative to the die center (where X and Y are the horizontal and vertical axis, respectively, measured in μm). Refer to Figure 19. 22/24 Doc ID 14140 Rev 2 STG4158 8 Revision history Revision history Table 12. Document revision history Date Revision 12-Nov-2007 1 Initial release 2 Added wafer JSTG4158-CD1, Section 7: Die description, updated Table 1, Section 2: Maximum rating, ECOPACK®, Figure 17, Figure 18 and Disclaimer, minor text corrections throughout document. 24-Apr-2012 Changes Doc ID 14140 Rev 2 23/24 STG4158 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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