STG4259BJR

STG4259 Low voltage 0.3Ω max dual SPDT switch with break-before-make feature and 15KV ESD protection Features ■ Wide operating voltage range: VCC (Opr) = 1.65 V to 4.8 V ■ Low power dissipation: ICC = 0.2 µA (max) at TA = 85°C ■ Low ON resistance VIN = 0V: – RON = 0.4 Ω (max TA = 25ºC) at VCC = 2.25 V – RON = 0.35 Ω (max TA = 25ºC) at VCC = 3.0 V – RON = 0.30 Ω (max TA = 25ºC) at VCC = 4.3 V ) s ( ct u d o r P e Flip-Chip11 ■ Separate supply voltage for switch and control pin ■ Separate control pin for each switch ■ Latch-up performance exceeds 100 mA per JESD 78, class II ■ ESD performance tested on common channels (D1 and D2 pins) – 9 kV IEC-61000-4-2 ESD, contact discharge – 15 kV IEC-61000-4-2 ESD, air gap discharge ) (s t c u d o r ■ P e t e l o ESD performance tested on all other pins – 8 kV IEC-61000-4-2 ESD, contact discharge – 500 V machine model (JESD22 A115-A) – 1500 V charged-device model (JESD22 C101) – 8 kV IEC-61000-4-2 ESD, air gap discharge s b O Table 1. t e l o Description s b O The STG4259 is a high-speed CMOS low voltage dual analog SPDT (single pole dual throw) switch or 2:1 multiplexer/ demultiplexer switch fabricated in silicon gate C2MOS technology. It is designed to operate from 1.65 V to 4.8 V, making this device ideal for portable applications. It offers low ON resistance (0.30 Ω) at VCC = 4.3 V. The SEL inputs are provided to control the switches. The switch S1 is ON (connected to common port D) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common port D) when the SEL input is held low and OFF (high impedance state exist between the two ports) when SEL is held high. Additional key features are fast switching speed, break-before-make delay time and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. Device summary Order code Package Packing STG4259BJR Flip-Chip11 Tape and Reel August 2007 Rev 4 1/19 www.st.com Contents STG4259 Contents 1 Logic diagram and pin-out information . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test circuits 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 2/19 s b O STG4259 1 Logic diagram and pin-out information Logic diagram and pin-out information Figure 1. Functional diagram SEL1 1S1 D1 1S2 2S2 Input equivalent circuit ) (s u d o r P e SEL2 Figure 2. ) s ( ct 2S1 D2 t e l o s b O t c u d o r P e t e l o SEL SEL s b O Table 2. Truth table SELn Switch nS1 Switch nS2 H ON OFF (1) L OFF (1) ON 1. High impedance 3/19 Logic diagram and pin-out information Figure 3. STG4259 Pin connection (bump side view) ) s ( ct Flip-Chip11 Table 3. Flip-Chip11 Symbol 4, 10, 6, 12 1S1, 1S2, 2S1, 2S2 9, 7 D1, D2 t e l o bs O ) 3, 1 SEL1, SEL2 11 t(s 2 uc 5 d o r P e t e l o s b O 4/19 VCC VL GND u d o r P e Pin description Name and function Independent channels Common channels Control Positive supply voltage Logic supply voltage Ground (0V) STG4259 2 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol VCC Value Supply voltage -0.5 to 5.5 VL Logic supply voltage -0.5 to 5.5 VI DC input voltage VIC DC control input voltage VO DC output voltage IIKC DC input diode current on control pin (VSEL< 0V) IIK DC input diode current (VSEL< 0V) IOK DC output diode current IO DC output current IOP ICC or IGND PD Tstg e t e ol TL 1. Parameter ) s ( ct u d o -0.5 to VCC + 0.5 Pr Unit V V V -0.5 to VL + 0.5 V -0.5 to VCC + 0.5 V - 50 mA ± 50 mA ± 20 mA ± 300 mA DC output current peak (pulse at 1ms, 10% duty cycle) ± 500 mA DC VCC or ground current ± 100 mA 500 mW -50 to 105 °C 260 °C u d o Power dissipation at TA = 70ºC (1) Pr o s b O ) s ( t c Storage temperature Lead temperature (10 sec) e t e l Derate above 70ºC by 18.5mW/C s b O 5/19 Maximum rating STG4259 Table 5. Recommended operating conditions Symbol Parameter Supply voltage VCC (1) Value Unit 1.65 to 4.8 V 1.65 to VCC V 0 to VCC V 0 to VL V VL Logic supply voltage VI Input voltage VIC Control input voltage VO Output voltage 0 to VCC V Top Operating temperature -40 to 85 °C dt/dv VL = 1.65 V to Input rise and fall time control 2.7 V input VL = 3.0 to 4.8 V 0 to 20 c u d 1. Truth table guaranteed: 1.65 V to 4.8 V e t e ol ) (s t c u d o r P e t e l o s b O 6/19 s b O ) s ( t ns/V 0 to 10 o r P STG4259 3 Electrical characteristics Electrical characteristics Table 6. DC specifications Test conditions Symbol Parameter VCC VL (V) (V) Value Min VIH High level input voltage 1.65 4.3 Typ Max Low level input voltage 1.65 4.3 1.25 1.25 2.3 - 2.7 1.75 1.75 3.0 - 3.6 2.35 2.35 4.3 2.8 3 ON resistance od 3.0 - 3.6 e t e ol t c u s b O VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA ) (s 3.7 4.3 1.8 ΔRON s b O e t e ol RFLAT od ON resistance match between channels (1) Pr 2.25 3 3.7 (s) Pr 0.6 0.8 0.8 1.05 1.05 1.5 1.5 0.49 0.65 0.85 0.30 0.40 0.50 0.25 0.35 0.45 0.22 0.32 0.42 0.21 0.30 0.40 V 3 VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA 3 mΩ 3 3 1.8 300 400 450 130 170 230 90 120 170 90 120 170 90 120 170 3 3.7 Ω 5 4.3 2.5 ON resistance flatness (2) Max t c u 2.8 0.6 2.3 - 2.7 1.8 RON Unit V 4.3 2.25 Min 1.65 - 1.95 1.65 - 1.95 VIL -40 to 85°C TA = 25°C VS = 0 V to 1.65 - 4.8 VCC IS = 100 mA 4.3 mΩ IOFF Sn OFF state leakage current 1.65 4.8 VS = 0 to VCC 1.65 - 4.8 VD = 0 to VCC -20 20 -300 300 nA ION Sn ON state leakage current 1.65 4.8 VS = 0 to 1.65 - 4.8 VCC VD = open -20 20 -100 100 nA 7/19 Electrical characteristics Table 6. STG4259 DC specifications (continued) ID D ON state leakage current 1.65 4.8 VS = open 1.65 - 4.8 VD = 0 to VCC ICC Quiescent supply current 1.654.8 1.65 - 4.8 ISEL SEL leakage current 1.654.8 1.65 - 4.8 -20 20 -100 100 nA VSEL= VCC or GND 0.05 0.05 -0.2 0.2 μA VSEL= 4.3V or GND -0.1 0.1 -1 1 μA 1. ΔRON = RON(Max) - RON(Min) 2. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal ranges. Test conditions Symbol Parameter VCC VL (V) (V) Value TA = 25°C Min 1.65 1.95 tPLH, tPHL Propagation delay Turn-ON time P e tOFF Turn-OFF time 2.3 - 2.7 1.65 4.8 3 - 3.6 2.3 - 2.7 1.65 4.8 3 - 3.6 s b O VS = VCC RL = 50 Ω CL = 30 pF VS = VCC RL = 50 Ω CL = 30 pF 4.3 1.65 1.95 tD Breakbefore-make time delay 2.3 - 2.7 1.65 4.8 3 - 3.6 CL = 35 pF RL = 50 Ω VS = VCC/2 4.3 1.651.95 Q Charge injection 2.3-2.7 3.0-3.3 3.6-4.3 8/19 -40 to 85°C o r P Typ Max Min Uni t Max 0.13 0.15 ns 0.16 4.3 1.65 1.95 du 0.16 O ) s ( t c du ro t e l o bs 3.0 - 3.3 1.65 1.95 ete ol 1.65 4.8 2.3 - 2.7 3.6 - 4.3 tON ) s ( ct AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns) ) Table 7. 95 123 95 48 62 70 33 43 55 29 38 40 12 15 70 12 16 55 13 17 40 13 17 35 10 66 10 28 10 18 10 12 ns ns ns 86 1.654.8 CL = 1nF VGEN = 0V 95 98 103 pC STG4259 Electrical characteristics ) Table 8. Analog switch characteristics (CL = 5pF, RL = 50Ω, TA = 25°C) Test conditions Symbol Parameter OIRR OFF isolation (1) Xtalk Crosstalk Value TA = 25°C -40 to 85°C Unit VCC VL (V) (V) 1.65 4.3 4.3 VS = 1VRMS f = 100kHz -71 dB 1.6 - 4.3 4.3 VS = 1VRMS f = 100 kHz -93 dB 4.3 RL = 600 Ω CL = 50 pF VS = VCC VPP f = 600Hz to 20 kHz 0.01 Min Typ Max Min Max ) s ( ct THD Total harmonic distortion BW -3dB bandwidth (switch ON) 1.65 4.3 4.3 RL = 50Ω CSEL Control pin input capacitance 1.8 - 4.3 1.8 4.3 VL = VCC 30 pF CSn Sn port capacitance 1.8 - 4.3 1.8 4.3 VL = VCC 95 pF CD D port capacitance when switch is enabled s b O 1.8 - 4.3 1.8 4.3 VL = VCC 230 pF 1. 2.3 - 4.3 t c u ) (s e t e ol % Pr u d o 40 MHz d o r OFF-isolation = 20 log10 (VD/VS), VD = output, VS = input to off switch P e t e l o s b O 9/19 Test circuits STG4259 4 Test circuits Figure 4. ON resistance Figure 5. Bandwidth ) s ( ct u d o Figure 6. OFF leakage Figure 7. t c u d o r t e l o Figure 8. s b O 10/19 OFF isolation Channel-to-channel crosstalk t e l o ) (s P e r P e s b O STG4259 Figure 9. Note: Test circuits Test circuit 1 CL = 5/35pF or equivalent: (includes jig capacitance) 2 RL = 50Ω or equivalent 3 RT = ZOUT of pulse generator (typically 50Ω) u d o r P e t e l o Figure 10. Break-before-make time delay ) (s ) s ( ct s b O t c u d o r P e t e l o s b O 11/19 Test circuits STG4259 Figure 11. Switching time and charge injection (VGEN = 0V, RGEN = 0Ω, RL = 1MΩ, CL = 100pF) ) s ( ct u d o Figure 12. Turn ON, turn OFF delay time r P e t e l o ) (s t c u d o r P e t e l o s b O 12/19 s b O STG4259 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 13. Flip-Chip11 package outline ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o 1. Drawing not to scale. 13/19 Package mechanical data Table 9. STG4259 Flip-Chip11 mechanical data Data book (mm) Drawing (mm) Dim. Min Typ Max Min Typ Max A 0.585 0.65 0.715 0.60 0.65 0.70 A1 0.21 0.25 0.29 0.22 0.25 0.28 0.38 0.4 0.42 A2 0.4 b 0.265 0.315 0.365 0.290 0.315 0.340 D 1.518 1.568 1.618 1.553 1.568 1.583 0.99 1 1.01 2.083 2.068 1.49 1.5 D1 E 1 2.018 E1 2.068 2.118 e 1.5 0.45 0.5 f 0.284 ccc 0.08 0.55 0.46 u d o 0.272 e t e ol ) s ( ct 0.5 Pr 0.284 2.118 1.51 0.54 0.292 0.08 The terminal A1 on the bumps side is identified by a distinguishing feature (for instance by a circular “clear area” - typically 0.1 mm diameter) and/or a missing bump. The terminal A1 on the backside of the product is identified by a distinguishing feature (for instance by a circular “dot” - typically 0.5 mm diameter). s b O Figure 14. Foot print recommendations ) (s t c u d o r P e t e l o s b O 14/19 STG4259 Package mechanical data Figure 15. Marking Dot, ST logo S2 = marking V = manufacturing Location yww = datecode (y = year, ww = week) S2V YWW ) s ( ct u d o Figure 16. Flip-Chip11 tape specification r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 15/19 Package mechanical data STG4259 Figure 17. Flip-Chip11 reel information ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 16/19 s b O STG4259 Package mechanical data Figure 18. Flip-Chip11 reel for carrier tape information ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 17/19 Revision history 6 STG4259 Revision history Table 10. Document revision history Date Revision Changes 03-Oct-2006 1 First release 16-Oct-2006 2 Schematic Figure 1 on page 3 updated 07-Aug-2007 3 Air discharge ESD rating updated 28-Aug-2007 4 Changed Figure 16 on page 15 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 18/19 s b O STG4259 ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. 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