STGAP2HS
Datasheet
Galvanically isolated 4 A single gate driver
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High voltage rail up to 1200 V
Driver current capability: 4 A sink/source @25°C
dV/dt transient immunity ±100 V/ns in full temperature range
Overall input-output propagation delay: 75 ns
Separate sink and source option for easy gate driving configuration
4 A Miller CLAMP dedicated pin option
UVLO function
Gate driving voltage up to 26 V
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Temperature shut-down protection
Standby function
6 kV galvanic isolation
UL 1577 recognized
Wide body SO-8W package
Application
Product status link
STGAP2HS
Product label
•
•
•
•
•
•
•
•
•
Motor driver for home appliances, factory automation, industrial drives and fans.
600/1200 V inverters
Battery chargers
Induction heating
Welding
UPS
Power supply units
DC-DC converters
Power Factor Correction
Description
The STGAP2HS is a single gate driver which provides galvanic isolation between the
gate driving channel and the low voltage control and interface circuitry.
The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the
device also suitable for mid and high power applications such as power conversion
and motor driver inverters in industrial applications. The device is available in
two different configurations. The configuration with separated output pins allows
to independently optimize turn-on and turn-off by using dedicated gate resistors.
The configuration featuring single output pin and Miller CLAMP function prevents
gate spikes during fast commutations in half-bridge topologies. Both configurations
provide high flexibility and bill of material reduction for external components.
The device integrates UVLO and thermal shutdown protection functions to facilitate
the design of highly reliable systems. Dual input pins allow the selection of signal
polarity control and implementation of HW interlocking protection to avoid crossconduction in case of controller malfunction. The input to output propagation delay
is less than 75 ns, which delivers high PWM control accuracy. A standby mode is
available to reduce idle power consumption.
DS13393 - Rev 5 - September 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
STGAP2HS
Block diagram
1
Block diagram
Figure 1. Block diagram - Single output and Miller Clamp configuration
VH
VDD
IN+
IN-
Control
Logic
I
S
O
L
A
T
I
O
N
GND
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GOUT
CLAMP
GNDISO
Floating ground A
+
VCLAMPth
Figure 2. Block diagram - Separate output configuration
VH
VDD
IN+
IN-
GND
DS13393 - Rev 5
Control
Logic
I
S
O
L
A
T
I
O
N
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GON
GOFF
GNDISO
Floating ground
page 2/22
STGAP2HS
Pin description and connection diagram
2
Pin description and connection diagram
Figure 3. Pin connection (top view) - Single output and Miller CLAMP option
VDD
1
8
GNDISO
IN+
2
7
CLAMP
IN-
3
6
GOUT
GND
4
5
VH
Figure 4. Pin connection (top view) - Separated outputs option
VDD
1
8
GNDISO
IN+
2
7
GOFF
IN-
3
6
GON
GND
4
5
VH
Table 1. Pin Description
Pin #
Figure 4
DS13393 - Rev 5
Pin Name
Figure 3
Type
Function
1
1
VDD
Power Supply
Driver logic supply voltage.
2
2
IN+
Logic Input
Driver logic input, active high.
3
3
IN-
Logic Input
Driver logic input, active low.
4
4
GND
Power Supply
Driver logic ground.
5
5
VH
Power Supply
Gate driving positive voltage supply.
-
6
GOUT
Analog Output
Sink/Source output.
-
7
CLAMP
Analog Output
Active Miller Clamp.
6
-
GON
Analog Output
Source output.
7
-
GOFF
Analog Output
Sink output.
8
8
GNDISO
Power Supply
Gate driving Isolated ground.
page 3/22
STGAP2HS
Electrical data
3
Electrical data
3.1
Absolute maximum ratings
Table 2. Absolute maximum ratings
Test
condition
Min.
Max.
Unit
Logic supply voltage vs. GND
-
-0.3
6.5
V
Logic pins voltage vs. GND
-
-0.3
6.5
V
Positive supply voltage (VH vs. GNDISO)
-
-0.3
28
V
Voltage on gate driver outputs (GON, GOFF, CLAMP VS. GNDISO)
-
-0.3
VH+0.3
V
TJ
Junction temperature
-
-40
150
°C
TS
Storage temperature
-
-50
150
°C
HBM (human body model)
-
Symbol
VDD
VLOGIC
VH
VOUT
ESD
3.2
Parameter
2
kV
Thermal data
Table 3. Thermal data
Symbol
Rth(JA)
3.3
Parameter
Thermal resistance junction to ambient
Package
Value
Unit
SO-8W
120
°C/W
Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Test conditions
Min.
Max.
Unit
Logic supply voltage vs. GND
-
3.1
5.5
V
Logic pins voltage vs. GND
-
0
5.5
V
VH
Positive supply voltage (VH vs. GNDISO)
-
Max(VHON)
26
V
FSW
Maximum switching frequency(1)
-
-
1
MHz
t OUT
Output pulse width (GOUT, GON-GOFF)
-
100
-
ns
Operating Junction Temperature
-
-40
125
°C
VDD
VLOGIC
TJ
Parameter
1. Actual limit depends on power dissipation and TJ.
DS13393 - Rev 5
page 4/22
STGAP2HS
Electrical characteristics
4
Electrical characteristics
Table 5. Electrical characteristics (TJ = 25°C, VH = 15 V, VDD = 5 V unless otherwise specified)
Symbol
Pin
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Dynamic charact eristics
tDon
IN+, IN-
Input to output propagation
delay ON
-
50
75
90
ns
tDoff
IN+, IN-
Input to output propagation
delay OFF
-
50
75
90
ns
tr
-
Rise time
CL = 4.7 nF
-
30
-
ns
tf
-
Fall time
See Figure 13
-
30
-
ns
PWD
-
-
-
-
20
ns
-
-
20
40
ns
100
-
-
V/ns
Pulse Width Distortion
|tDon-tDoff|
tdeglitch
IN+, IN-
CMTI (1)
-
Common-mode transient
immunity, |dVISO/dt|
VHon
-
VH UVLO turn-on threshold
-
8.6
9.1
9.6
V
VHoff
-
VH UVLO turn-off threshold
-
7.9
8.4
8.9
V
VHhyst
-
VH UVLO hysteresis
-
600
750
950
mV
IQHU
-
VH undervoltage quiescent
supply current
VH = 7V
-
1.3
1.8
mA
IQH
-
VH quiescent supply current
-
-
1.3
1.8
mA
IQHSBY
-
Standby VH quiescent supply
current
Standby mode
-
400
550
µA
SafeClp
-
GOFF active clamp
-
2
2.3
V
IQDD
-
VDD quiescent supply current
-
-
1.0
1.3
mA
IQDDSBY
-
Standby VDD quiescent
supply current
Standby mode
-
40
65
µA
Inputs deglitch filter
VCM = 1500 V,
See Figure 12
Supply voltage
IGOFF = 0.2 A;
VH floating
Logic Inputs
Vil
IN+, IN-
Low level logic threshold
voltage
-
0.29·VDD
0.33·VDD
0.37·VDD
V
Vih
IN+, IN-
High level logic threshold
voltage
-
0.62·VDD
0.66·VDD
0.70·VDD
V
IINh
IN+, IN-
INx logic “1” input bias current
INx = 5 V
33
50
70
µA
IINl
IN+, IN-
INx logic “0” input bias current
INx = GND
-
-
1
µA
Rpd
IN+, IN-
Inputs pull-down resistors
INx = 5 V
70
100
150
kΩ
TJ = 25°C
-
4
-
A
(1)
3
-
5
A
IGON = 100 mA
VH-0.15
VH-0.125
-
V
Driver buffer section
IGON
VGONH
DS13393 - Rev 5
-
-
Source short circuit current
Source output high level
voltage
TJ = -40 to +125°C
page 5/22
STGAP2HS
Electrical characteristics
Symbol
Pin
Parameter
RGON
-
Source RDS_ON
IGOFF
-
Sink short-circuit current
Test conditions
Min.
Typ.
Max.
Unit
IGON = 100 mA
-
1.25
1.5
Ω
TJ = 25°C
-
4
-
(1)
3
-
5.5
TJ = -40 to +125°C
A
VGOFFL
-
Sink output low level voltage
IGOFF = 100 mA
-
100
120
mV
RGOFF
-
Sink RDS_ON
IGOFF = 100 mA
-
1.0
1.2
Ω
-
CLAMP voltage threshold
VCLAMP vs.GNDISO
1.3
2
2.6
V
-
4
-
(1)
2
-
5
Miller Clamp
VCLAMPth
VCLAMP = 15V
ICLAMP
-
CLAMP short-circuit current
TJ = 25°C
TJ = -40 to +125°C
A
VCLAMP_L
-
CLAMP low level output
voltage
ICLAMP = 100mA
-
96
115
mV
RCLAMP
-
CLAMP RDS_ON
ICLAMP = 100mA
-
0.96
1.15
Ω
Over-temperature protection
TSD
-
Shutdown temperature
-
170
-
-
°C
Thys
-
Temperature hysteresis
-
-
20
-
°C
tSTBY
-
Standby time
See Section 6.3
200
280
500
µs
tWUP
-
Wake-up time
See Section 6.3
10
20
35
µs
tawake
-
Wake-up delay
See Section 6.3
90
140
200
µs
tstbyfilt
-
Standby filter
See Section 6.3
200
280
800
ns
Standby
1. Characterization data, not tested in production.
DS13393 - Rev 5
page 6/22
STGAP2HS
Isolation
5
Isolation
Table 6. Isolation and safety-related specifications
Parameter
Clearance
(Minimum External Air Gap)
Creepage (*)
(Minimum External Tracking)
Comparative Tracking Index (Tracking
Resistance)
Isolation Group
Symbol
Value
Unit
Conditions
CLR
8
mm
Measured from input terminals to output terminals, shortest
distance through air
CPG
8
mm
Measured from input terminals to output terminals, shortest
distance path along body
CTI
≥ 400
V
DIN IEC 112/VDE 0303 Part 1
-
II
-
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 7. Isolation characteristics
Parameter
Maximum Working Isolation Voltage
Symbol
Test Conditions
Characteristic
Unit
VIORM
-
1200
VPEAK
1920
VPEAK
2250
VPEAK
Method a, Type test
VPR = VIORM ×1.6, tm = 10 s
Input to Output test voltage
VPR
In accordance with VDE 0884-11
Partial discharge < 5 pC
Method b1, 100 % Production test
VPR = VIORM×1.875, tm = 1 s
Partial discharge < 5 pC
Transient Overvoltage (Highest
Allowable Overvoltage)
VIOTM
tini = 60 s Type test
6000
VPEAK
Maximum Surge TestVoltage
VIOSM
Type test
6000
VPEAK
VIO = 500 V; Type test
>109
Ω
RIO
Isolation Resistance
Table 8. Isolation voltage as per UL 1577
Parameter
Symbol
Characteristic
Unit
Isolation Withstand Voltage, 1min (Type test)
VISO
3535/5000
VRMS/VPEAK
Isolation TestVoltage, 1sec (100% production)
VISOtest
4242/6000
VRMS/VPEAK
Recognized under the UL 1577 Component Recognition Program - file number E362869
DS13393 - Rev 5
page 7/22
STGAP2HS
Functional description
6
Functional description
6.1
Gate driving power supply and UVLO
The STGAP2HS is a flexible and compact gate driver with 4 A output current and rail-to-rail outputs. The device
allows implementation of either unipolar or bipolar gate driving.
Figure 5. Power supply configuration for unipolar and bipolar gate driving
Unipolar gate driving
VDD
Bipolar gate driving
VDD
VDD
VDD
1uF
100nF
1uF
VH
IN+
IN-
GND
I
S
O
L
A
T
I
O
N
100nF
1uF
+
VH
100nF
VH
IN+
GON
GOFF
GNDISO
IN-
GND
I
S
O
L
A
T
I
O
N
100nF
1uF
+
VH
GON
GOFF
1uF
+
VL
GNDISO
Undervoltage protection is available on VH supply pin. A fixed hysteresis sets the turn-off threshold, thus avoiding
intermittent operation.
When VH voltage falls below the VHoff threshold, the output buffer enters a “safe state”. When VH voltage
reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input
pins status.
The VDD and VH supply pins must be properly filtered with local bypass capacitors. The use of capacitors with
different values in parallel provides both local storage for impulsive current supply and high-frequency filtering.
The best filtering is obtained by using low-ESR SMT ceramic capacitors and are therefore recommended. A 100
nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor with
value in the range between 1 µF and 10 µF should be placed close to it.
6.2
Power-up, power-down and “safe state”
The following conditions define the “safe state”:
•
GOFF = ON state;
•
GON = High Impedance;
•
CLAMP = ON state (for STGAP2HSC);
Such conditions are maintained at power-up of the isolated side (VH < VHon) and during whole device power
down phase (VH < VHoff), regardless of the value of the input pins.
The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH
voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH positive supply pin is floating or
not supplied the GOFF pin is therefore clamped to a voltage smaller than SafeClp.
If the supply voltage VDD of the control section of the device is not supplied, the output is put in safe state, and
remains in such condition until the VDD voltage returns within operative conditions.
After power-up of both isolated and low voltage sides, the device output state depends on the status of the input
pins.
DS13393 - Rev 5
page 8/22
STGAP2HS
Control inputs
6.3
Control inputs
The device is controlled through the IN+ and IN- logic inputs, in accordance with the truth table below.
Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state")
Input pins
Output pins
IN+
IN-
GON
GOFF
L
L
OFF
ON
H
L
ON
OFF
L
H
OFF
ON
H
H
OFF
ON
A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing noise
spikes potentially present in the application from generating unwanted commutations.
6.4
Miller Clamp function
The Miller clamp function allows the control of the Miller current during the power stage switching in half-bridge
configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced
turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the CGD
capacitance.
During the turn-off period the gate of the external switch is monitored through the CLAMP pin. The CLAMP switch
is activated when gate voltage goes below the voltage threshold, VCLAMPth, thus creating a low impedance path
between the switch gate and the GNDISO pin.
6.5
Watchdog
The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side,
for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced in “safe
state” until communication link is properly established again.
6.6
Thermal shutdown protection
The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature
threshold, the device is forced in “safe state”. The device operation is restored as soon as the junction
temperature is lower than TSD-Thys.
DS13393 - Rev 5
page 9/22
STGAP2HS
Standby function
6.7
Standby function
In order to reduce the power consumption of both control interface and gate driving sides the device can be put in
standby mode. In standby mode the quiescent current from VDD and VH supply pins is reduced to IQDDSBY and
IQHSBY respectively, and the output remains in “safe state” (the output is actively forced low).
The way to enter standby is to keep both IN+ and IN- high (“standby” value) for a time longer than tSTBY. During
stand-by the inputs can change from the “standby” value.
To exit stand-by, IN+ and IN- must be put in any combination different from the “standby” value for a time longer
than tstbyfilt, and then in the “standby” value for a time t such that tWUP tSTBY
duration
too short
duration too long
“stand-by”
“stand-by”
tWUP < t < tSTBY
t = tawake
“stand-by”
Device status
ACTIVE
STAND-BY
ACTIVE
Output
ACTIVE
SAFE-STATE
ACTIVE
page 10/22
STGAP2HS
Typical application diagram
7
Typical application diagram
Figure 7. Typical application diagram - Separated outputs
VDD
HV_BUS
VDD
VH_HS
UVLO
VDD
IN+
R
C
IN-
VDD
R
Control
Logic
C
GND
HIN
MCU
VH
I
S
O
L
A
T
I
O
N
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GON
GOFF
GND_HS
Floating ground
GNDISO
VDD
LIN
Load_ Phase
VDD
VH_LS
VH
UVLO
VDD
IN+
R
C
INR
Control
Logic
C
GND
I
S
O
L
A
T
I
O
N
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GON
GOFF
GND_LS
GNDISO
Floating ground
GND_PWR
Figure 8. Typical application diagram - Separated outputs and negative gate driving
VDD
HV_BUS
VDD
VH_HS
UVLO
VDD
IN+
R
C
IN-
VDD
R
Control
Logic
C
GND
VH
I
S
O
L
A
T
I
O
N
+
UVLO
VH
VH
Floating
Section
Control
Logic
Level
Shifter
GON
GOFF
VL_HS
Floating ground
GND_HS
GNDISO
VL
HIN
MCU
+
VDD
LIN
Load_ Phase
VDD
VH
VH_LS
UVLO
VDD
IN+
R
C
INR
C
GND
Control
Logic
I
S
O
L
A
T
I
O
N
+
UVLO
VH
VH
Floating
Section
Control
Logic
Level
Shifter
GON
GOFF
VL_LS
Floating ground
GNDISO
VL
DS13393 - Rev 5
+
GND_LS
GND_PWR
page 11/22
STGAP2HS
Typical application diagram
Figure 9. Typical application diagram - Miller Clamp
VDD
VH_HS
HV_BUS
VDD
VH
IN+
R
C
IN-
VDD
R
Control
Logic
C
I
S
O
L
A
T
I
O
N
GND
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GOUT
CLAMP
GND_HS
Floating ground A
GNDISO
+
VCLAMPth
HIN
MCU
VDD
LIN
Load_ Phase
VH_LS
VDD
VH
IN+
R
C
INR
Control
Logic
C
I
S
O
L
A
T
I
O
N
GND
UVLO
VH
Floating
Section
Control
Logic
Level
Shifter
GOUT
CLAMP
GND_LS
Floating ground A
GNDISO
+
GND_PWR
VCLAMPth
Figure 10. Typical application diagram - Miller Clamp and negative gate driving
VDD
HV_BUS
VDD
VH_HS
VH
IN+
R
C
IN-
VDD
R
Control
Logic
C
I
S
O
L
A
T
I
O
N
GND
UVLO
VH
+
Floating
Section
Control
Logic
VH
GOUT
Level
Shifter
CLAMP
VL_HS
Floating ground A
GND_HS
GNDISO
+
VCLAMPth
HIN
MCU
VL
+
VDD
LIN
Load_ Phase
VDD
VH_LS
VH
IN+
R
C
INR
C
GND
Control
Logic
I
S
O
L
A
T
I
O
N
UVLO
VH
+
Floating
Section
Control
Logic
Level
Shifter
CLAMP
VL_LS
Floating ground A
GNDISO
+
VCLAMPth
DS13393 - Rev 5
VH
GOUT
VL
+
GND_LS
GND_PWR
page 12/22
STGAP2HS
Layout
8
Layout
8.1
Layout guidelines and considerations
In order to optimize the PCB layout, the following considerations should be taken into account:
•
SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to
each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and
GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to
provide local storage for pulsed current, a second capacitor with a value between 1 µF and 10 µF should
also be placed close to the supply pins.
•
It is good practice to add filtering capacitors close to logic inputs of the device (IN+, IN-), particularly for fast
switching or noisy applications.
•
The power transistors must be placed as close as possible to the gate driver to minimize the gate loop area
and inductance that might carry noise or cause ringing.
•
To avoid degradation of the isolation between the primary and secondary side of the driver, there should not
be any trace or conductive area below the driver.
•
If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground
or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to
maximize thermal conductivity.
8.2
Layout example
An example of STGAP2HSC half-bridge suggested PCB layout with main signals highlighted by different colors
is shown in Figure 11. It is recommended to follow this example for correct positioning and connection of filtering
capacitors.
Figure 11. Half-bridge suggested PCB layout
CVH1
RIN
CIN
RON
CVH2
Q1
DBOOT
U1
CG
DOFF
CIN
RIN
CVDD1
G1
ROFF
RBOOT
S1
G2
Q2
ROFF
RIN
CIN
DOFF
CIN
U2
CVH2
TOP
DS13393 - Rev 5
CG
CVH1
RIN
CVDD1
D1
D2
RON
S2
BOTTOM
page 13/22
STGAP2HS
Testing and characterization information
9
Testing and characterization information
Figure 12. CMTI test circuit
VDD
+
VDD
VH
+
IN+
S1
I
S
O
L
A
T
I
O
N
-
IN-
GON
Output V out
monitoring node
+
VH
GOFF
GNDISO
GND
G1
Figure 13. Timings definition
IN+
50%
50%
IN-
50%
tr
tf
90%
GON-GOFF
DS13393 - Rev 5
tr
90%
t Doff
tf
90%
10%
10%
t Don
50%
90%
10%
t Don
10%
t Doff
page 14/22
STGAP2HS
Package information
10
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
10.1
SO-8W package information
Table 10. SO-8W package dimensions
Symbol
Dimensions (mm)
Min.
Typ.
Max
A
2.34
2.64
A1
0.1
0.3
b
0.3
0.51
c
0.2
0.33
D(1)
5.64
6.05
e
1.27 BSC
E1
7.39
7.59
E
10.11
10.52
L
0.61
0.91
h
0.25
0.76
Ɵ
0°
8°
aaa
0.25
bbb
0.25
ccc
0.1
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
DS13393 - Rev 5
page 15/22
STGAP2HS
SO-8W suggested land pattern
A
0.01
Figure 14. SO-8W mechanical data
c
L
A1
8X b
D
h X 45°
E
E1
e/2
6X e
10.2
SO-8W suggested land pattern
Figure 15. SO-8W suggested land pattern
0.6 (x8)
1.27
8.00
1.5
11.00
DS13393 - Rev 5
page 16/22
STGAP2HS
Ordering information
11
Ordering information
Table 11. Device summary
DS13393 - Rev 5
Order code
Output configuration
Package marking
Package
Packaging
STGAP2HSMTR
GON-GOFF
GAP2HS2
SO-8W
Tape and Reel
STGAP2HSCMTR
GOUT-CLAMP
GAP2HSC2
SO-8W
Tape and Reel
page 17/22
STGAP2HS
Revision history
Table 12. Document revision history
DS13393 - Rev 5
Date
Version
Changes
12-Aug-2020
1
Initial release.
01-Sep-2020
2
Updated some parameters in Table 5; updated some symbols in Table 10
13-Aug-2021
3
Updated VDD parameter in Table 4 ; updated Isolation Resistance Test
condition parameter in Table 7; updated title of Table 8; changed Figure 15
and Figure 10; updated Table 3; updated Driver buffer section and Standby in
Table 5.
15-Oct-2021
4
Updated Table 5 with missing notes.
29-Sep-2022
5
Added UL file certification
page 18/22
STGAP2HS
Contents
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1
Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2
Power-up, power-down and “safe state”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.3
Control inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.4
Miller Clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.5
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.6
Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.7
Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
8
Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
8.1
Layout guidelines and considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.2
Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
10
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
11
10.1
SO-8W package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.2
SO-8W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DS13393 - Rev 5
page 19/22
STGAP2HS
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics (TJ = 25°C, VH = 15 V, VDD = 5 V unless otherwise specified)
Isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Isolation voltage as per UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs truth table (applicable when device is not in UVLO or "safe state") . . . . . . . . . .
SO-8W package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS13393 - Rev 5
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15
17
18
page 20/22
STGAP2HS
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
DS13393 - Rev 5
Block diagram - Single output and Miller Clamp configuration . . . . . . . . . .
Block diagram - Separate output configuration . . . . . . . . . . . . . . . . . . . .
Pin connection (top view) - Single output and Miller CLAMP option . . . . . .
Pin connection (top view) - Separated outputs option. . . . . . . . . . . . . . . .
Power supply configuration for unipolar and bipolar gate driving . . . . . . . .
Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical application diagram - Separated outputs . . . . . . . . . . . . . . . . . . .
Typical application diagram - Separated outputs and negative gate driving .
Typical application diagram - Miller Clamp . . . . . . . . . . . . . . . . . . . . . . .
Typical application diagram - Miller Clamp and negative gate driving . . . . .
Half-bridge suggested PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8W mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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. 2
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. 8
10
11
11
12
12
13
14
14
16
16
page 21/22
STGAP2HS
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS13393 - Rev 5
page 22/22
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