STGAP2SICSNTR

STGAP2SICSN Datasheet Galvanically isolated 4 A single gate driver for SiC MOSFETs Features • • • • • • • • • • • • High voltage rail up to 1700 V Driver current capability: 4 A sink/source @25 °C dV/dt transient immunity ±100 V/ns in full temperature range Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP dedicated pin option UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function 4.8 kVPK isolation • • UL 1577 recognized Narrow body SO-8 Application Product status link STGAP2SICSN Product label • • • • • • • • • Motor driver for home appliances, factory automation, industrial drives and fans. 600/1200 V inverters Battery chargers Induction heating Welding UPS Power supply units DC-DC converters Power Factor Correction Description The STGAP2SICSN is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. DS13757 - Rev 3 - September 2022 For further information contact your local STMicroelectronics sales office. www.st.com STGAP2SICSN The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption. DS13757 - Rev 3 page 2/24 STGAP2SICSN Block diagram 1 Block diagram Figure 1. Block diagram - Single output and Miller Clamp configuration VH VDD IN+ IN- Control Logic I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GNDISO Floating ground A + VCLAMPth Figure 2. Block diagram - Separate outputs configuration VH VDD IN+ IN- GND DS13757 - Rev 3 Control Logic I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GON GOFF GNDISO Floating ground page 3/24 STGAP2SICSN Pin description and connection diagram 2 Pin description and connection diagram Figure 3. Pin connection (top view), Separated outputs option VDD 1 8 GNDISO IN+ 2 7 GOFF IN- 3 6 GON GND 4 5 VH Figure 4. Pin connection (top view), Single output and Miller CLAMP option VDD 1 8 GNDISO IN+ 2 7 CLAMP IN- 3 6 GOUT GND 4 5 VH Table 1. Pin Description Pin # Type Function Figure 4 1 1 VDD Power supply Driver logic supply voltage. 2 2 IN+ Logic input Driver logic input, active high. 3 3 IN- Logic input Driver logic input, active low. 4 4 GND Power supply Driver logic ground. 5 5 VH Power supply Gate driving positive voltage supply. 6 GOUT Analog output Sink/Source output. 7 CLAMP Analog output Active Miller Clamp. 6 GON Analog output Source output. 7 GOFF Analog output Sink output. GNDISO Power supply Gate driving Isolated ground. 8 DS13757 - Rev 3 Pin name Figure 3 8 page 4/24 STGAP2SICSN Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Min. Max. Unit VDD Logic supply voltage vs. GND -0.3 6.5 V VLOGIC Logic pins voltage vs. GND -0.3 6.5 V -0.3 28 V Positive supply voltage VH 3.2 Test condition Parameter (VH vs. GNDISO) VOUT Voltage on gate driver outputs (GON, GOFF, CLAMP vs. GNDISO) - 0.3 VH + 0.3 V TJ Junction temperature -40 150 °C TS Storage temperature -50 150 °C ESD HBM (human body model) 2 kV Thermal data Table 3. Thermal data Symbol Rth(JA) 3.3 Parameter Thermal resistance junction to ambient Package Value Unit SO-8 123 °C/W Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter VDD Logic supply voltage vs. GND VLOGIC Logic pins voltage vs. GND VH Test conditions Positive supply voltage (VH vs. GNDISO) Min. Max. Unit 3.1 5.5 V 0 5.5 V Max(VHon) 26 V -1700 +1700 V 1 MHz VISO-OP Input to output operative voltage (GND to GNDISO) FSW Maximum switching frequency.(1) tOUT Output Pulse width 100 TJ Operating Junction Temperature -40 DC or peak ns 125 °C 1. Actual limit depends on power dissipation and TJ DS13757 - Rev 3 page 5/24 STGAP2SICSN Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics (TJ = 25°C, VH = 18 V, VDD = 5 V unless otherwise specified) Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics tDon IN+, IN- Input to output propagation delay ON 50 75 90 ns tDoff IN+, IN- Input to output propagation delay OFF 50 75 90 ns tr Rise time tf Fall time CL= 4.7 nF see Figure 12 30 ns 30 ns Pulse Width Distortion | tDon - tDoff| PWD tdeglitch IN+, IN- Inputs deglitch filter Common-mode transient immunity, |dVISO/dt| CMTI(1) 20 VCM = 1500 V, see Figure 13 20 ns 40 ns 100 V/ns Supply voltage VHon VH VH UVLO turn-on threshold 14.6 15.5 16.4 V VHoff VH VH UVLO turn-off threshold 13.9 14.8 15.7 V VHhyst VH VH UVLO hysteresis 600 750 950 mV IQHU VH VH undervoltage quiescent supply current 1.3 1.8 mA IQH VH VH quiescent supply current 1.3 1.8 mA IQHSBY VH Standby VH quiescent supply current 400 550 µA 2 2.3 V 1.0 1.3 mA 40 65 µA SafeClp GOUT / GOFF GOFF active clamp VH = 7.0 V Standby mode IGOFF = 0.2 A; VH floating IQDD VDD VDD quiescent supply current IQDDSBY VDD Standby VDD quiescent supply current Vil IN+, IN- Low-level logic threshold voltage 0.29·VDD 0.33·VDD 0.37·VDD V Vih IN+, IN- High-level logic threshold voltage 0.62·VDD 0.66·VDD 0.70·VDD V IINh IN+, IN- INx logic “1” input bias current INx = 5 V 33 50 70 µA IINl IN+, IN- INx logic “0” input bias current INx = GND 1 µA Rpd IN+, IN- Inputs pull-down resistors INx = 5 V 150 kΩ Source short-circuit current TJ = 25 °C Standby mode Logic inputs 70 100 Driver buffer section IGON DS13757 - Rev 3 GOUT / GON 4 A page 6/24 STGAP2SICSN Electrical characteristics Symbol Pin Parameter Test conditions IGON GOUT / GON Source short-circuit current TJ = -40 ÷ +125 °C(1) VGONH GOUT / GON Source output high-level voltage IGON = 100 mA RGON GOUT / GON Source RDS_ON IGON = 100 mA IGOFF GOUT / GOFF Sink short-circuit current Sink output low-level voltage VGOFFL GOUT / GOFF RGOFF GOUT / GOFF Sink RDS_ON Min. Typ. 3 Max. Unit 5 VH-0.15 VH-0.125 1.25 TJ = 25 °C V 1.5 Ω 4 TJ = -40 ÷ +125 °C (1) 3 A 5.5 IGOFF = 100 mA 110 120 mV IGOFF = 100 mA 1.1 1.2 Ω 2 2.6 V Miller clamp function VCLAMPth CLAMP CLAMP voltage threshold VCLAMP vs. GNDISO 1.3 VCLAMP = 15 V ICLAMP CLAMP CLAMP short-circuit current A TJ = 25 °C TJ = -40 ÷ +125 °C 4 (1) 2 5 VCLAMP_L CLAMP CLAMP low-level output voltage ICLAMP = 100 mA 96 115 mV RCLAMP CLAMP CLAMP RDS_ON ICLAMP = 100 mA 0.96 1.15 Ω Overtemperature protection TSD Shutdown temperature(1) Thys Temperature hysteresis(1) 170 °C 20 °C Standby tSTBY Standby time See Section 5.7 200 280 500 µs tWUP Wake-up time See Section 5.7 10 20 35 µs tawake Wake-up delay See Section 5.7 90 140 200 µs tstbyfilt Standby filter See Section 5.7 200 280 800 ns 1. Characterization data, not tested in production. Table 6. Isolation related package specifications Parameter Clearance (Minimum External Air Gap ) Creepage (*) (Minimum External Tracking) Comparative Tracking Index (Tracking Resistance) Isolation Group DS13757 - Rev 3 Symbol Value Unit CLR 4 mm Measured from input terminals to output terminals, shortest distance through air CPG 4 mm Measured from input terminals to output terminals, shortest distance path along body CTI ≥ 400 V II Conditions DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) page 7/24 STGAP2SICSN Electrical characteristics Table 7. Isolation characteristics Parameter Symbol Test conditions Characteristic Unit 2720 VPEAK 3200 VPEAK Method a, Type test VPR = 2720, tm = 10 s Input to Output test voltage Partial discharge < 5 pC VPR In accordance with VDE 0884-11 Method b1, 100 % Production test VPR = 3200, tm = 1 s Partial discharge < 5 pC Transient Overvoltage (Highest Allowable Overvoltage) Maximum Surge Test Voltage VIOTM tini = 60 s, Type test 4800 VPEAK VIOSM Type test 4800 VPEAK VIO = 500 V , Type test >109 Ω RIO Isolation Resistance Table 8. UL 1577 Tests Description Isolation Withstand Voltage, 1min (Type test) Isolation Voltage, 1sec (100% production) Symbol Characteristic Unit VISO 2828/4000 Vrms/ PEAK VISOtest 3394/4800 Vrms/ PEAK Recognized under the UL 1577 Component Recognition Program - file number E362869 DS13757 - Rev 3 page 8/24 STGAP2SICSN Functional Description 5 Functional Description 5.1 Gate driving power supply and UVLO The STGAP2SiCSN is a flexible and compact gate driver with 4 A output current and rail-to-rail outputs. The device allows implementation of either unipolar or bipolar gate driving. Figure 5. Power supply configuration for unipolar and bipolar gate driving Unipolar gate driving VDD Bipolar gate driving VDD VDD VDD 1uF 100nF 1uF VH IN+ IN- GND I S O L A T I O N 100nF 1uF + VH 100nF VH IN+ GON GOFF GNDISO IN- GND I S O L A T I O N 100nF 1uF + VH GON GOFF 1uF + VL GNDISO Undervoltage protection is available on VH supply pin. A fixed hysteresis sets the turn-off threshold, thus avoiding intermittent operation. When VH voltage goes below the VHoff threshold, the output buffer goes into “safe state”. When VH voltage reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input pins status. The VDD and VH supply pins must be properly filtered with local bypass capacitors. The use of capacitors with different values in parallel provides both local storage for impulsive current supply and high-frequency filtering. The best filtering is obtained by using low-ESR SMT ceramic capacitors, which are therefore recommended. A 100 nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor with a value in the range between 1 µF and 10 µF should be placed close to it. 5.2 Power-up, power-down and ‘safe state’ The following conditions define the “safe state”: • GOFF = ON state; • GON = High Impedance; • CLAMP = ON state (for STGAP2SiCSNC); Such conditions are maintained at power-up of the isolated side (VH < VHon) and during whole device powerdown phase (VH < VHoff), regardless of the value of the input pins. The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH positive supply pin is floating or not supplied, the GOFF pin is therefore clamped to a voltage smaller than SafeClp. If the supply voltage VDD of the control section of the device is not supplied, the output is put into safe state, and remains in such condition until the VDD voltage returns within operative conditions. After power-up of both isolated and low voltage side, the device output state depends on the input pins’ status. DS13757 - Rev 3 page 9/24 STGAP2SICSN Control inputs 5.3 Control inputs The device is controlled through the IN+ and IN- logic inputs, in accordance with the truth table described in Table 9. Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state") Input pins Output pins IN+ IN- GON GOFF L L OFF ON H L ON OFF L H OFF ON H H OFF ON A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing noise spikes potentially present in the application from generating unwanted commutations. 5.4 Miller Clamp function The Miller Clamp function allows the control of the Miller current during the power stage switching in half-bridge configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the CGD capacitance. During the turn-off period the gate of the external switch is monitored through the CLAMP pin. The CLAMP switch is activated when gate voltage goes below the voltage threshold, VCLAMPth, thus creating a low impedance path between the switch gate and the GNDISO pin. 5.5 Watchdog The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side, for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced in “safe state” until communication link is properly established again. 5.6 Thermal shutdown protection The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature threshold, the device is forced into “safe state”. The device operation is restored as soon as the junction temperature is lower than TSD - Thys. DS13757 - Rev 3 page 10/24 STGAP2SICSN Standby function 5.7 Standby function In order to reduce the power consumption of both control interface and gate driving sides the device can be put in standby mode. In standby mode the quiescent current from VDD and VH supply pins is reduced to IQDDSBY and IQHSBY respectively, and the output remains in ‘safe state’ (the output is actively forced low). The way to enter standby is to keep both IN+ and IN- high (“standby” value) for a time longer than tSTBY. During standby the inputs can change from the “standby” value. To exit standby, IN+ and IN- must be put in any combination different from the “standby” value for a time longer than tstbyfilt , and then in the “standby” value for a time t such that tWUP< t < tSTBY. When the input configuration is changed from the “standby” value the output is enabled and set according to inputs state after a time tawake. Figure 6. Standby state sequences Sequence to enter stand-by mode “stand-by”: IN+ = IN- = HIGH t = tSTBY t < tSTBY is any different combination duration too short IN+ & IN- “stand-by” “stand-by” Device status ACTIVE STAND-BY Output ACTIVE SAFE-STATE Sequence to exit stand-by mode t = tSTBY IN+ & IN- DS13757 - Rev 3 “stand-by” t > tstbyfilt t < tWUP t > tSTBY duration too short duration too long “stand-by” “stand-by” tWUP < t < tSTBY t = tawake “stand-by” Device status ACTIVE STAND-BY ACTIVE Output ACTIVE SAFE-STATE ACTIVE page 11/24 STGAP2SICSN Typical application diagram 6 Typical application diagram Figure 7. Typical application diagram - Separated outputs VDD HV_BUS VDD VH_HS UVLO VDD IN+ R C IN- VDD R Control Logic C GND HIN MCU VH I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GON GOFF GND_HS Floating ground GNDISO VDD LIN Load_ Phase VDD VH_LS VH UVLO VDD IN+ R C INR Control Logic C GND I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GON GOFF GND_LS GNDISO Floating ground GND_PWR Figure 8. Typical application diagram - Separated outputs and negative gate driving VDD HV_BUS VDD VH_HS UVLO VDD IN+ R C IN- VDD R Control Logic C GND VH I S O L A T I O N + UVLO VH VH Floating Section Control Logic Level Shifter GON GOFF VL_HS Floating ground GND_HS GNDISO VL HIN MCU + VDD LIN Load_ Phase VDD VH VH_LS UVLO VDD IN+ R C INR C GND Control Logic I S O L A T I O N + UVLO VH VH Floating Section Control Logic Level Shifter GON GOFF VL_LS Floating ground GNDISO VL DS13757 - Rev 3 + GND_LS GND_PWR page 12/24 STGAP2SICSN Typical application diagram Figure 9. Typical application diagram - Miller Clamp VDD VH_HS HV_BUS VDD VH IN+ R C IN- VDD R Control Logic C I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GND_HS Floating ground A GNDISO + VCLAMPth HIN MCU VDD LIN Load_ Phase VH_LS VDD VH IN+ R C INR Control Logic C I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GND_LS Floating ground A GNDISO + GND_PWR VCLAMPth Figure 10. Typical application diagram - Miller Clamp and negative gate driving VDD HV_BUS VDD VH_HS VH IN+ R C IN- VDD R Control Logic C I S O L A T I O N GND UVLO VH + Floating Section Control Logic VH GOUT Level Shifter CLAMP VL_HS Floating ground A GND_HS GNDISO + VCLAMPth HIN MCU VL + VDD LIN Load_ Phase VDD VH_LS VH IN+ R C INR C GND Control Logic I S O L A T I O N UVLO VH + Floating Section Control Logic Level Shifter CLAMP VL_LS Floating ground A GNDISO + VCLAMPth DS13757 - Rev 3 VH GOUT VL + GND_LS GND_PWR page 13/24 STGAP2SICSN Layout 7 Layout 7.1 Layout guidelines and considerations In order to optimize the PCB layout, the following considerations should be taken into account: • • • • • 7.2 SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to each supply rail pin. A 100 nF capacitor must be placed between VDD and GND and between VH and GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF should also be placed close to the supply pins. As a good practice, it is suggested to add filtering capacitors close to logic inputs of the device (IN+, IN-), in particular for fast switching or noisy applications. The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop area and inductance that might lead to noise or ringing. To avoid degradation of the isolation between the primary and secondary side of the driver, there should not be any trace or conductive area below the driver. If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity. Layout example An example of the STGAP2SiCSNC half-bridge suggested PCB layout with main signals highlighted by different colors is shown in Figure 11. It is recommended to follow this example for proper positioning and connection of filtering capacitors. Figure 11. Half-bridge suggested PCB layout CVH1 RIN CIN RON CVH2 Q1 DBOOT U1 CG DOFF CIN RIN CVDD1 G1 ROFF RBOOT S1 G2 Q2 ROFF RIN CIN DOFF CIN U2 CVH2 TOP DS13757 - Rev 3 CG CVH1 RIN CVDD1 D1 D2 RON S2 BOTTOM page 14/24 STGAP2SICSN Testing and characterization information 8 Testing and characterization information Figure 12. Timings definition IN+ 50% 50% IN- 50% tr tf 90% GON-GOFF 50% tr 90% 10% 10% t Doff t Don tf 90% 90% 10% 10% t Doff t Don Figure 13. CMTI test circuit VDD + VDD + S1 VH IN+ - IN- I S O L A T I O N GND GON Output V out monitoring node + VH GOFF GNDISO G1 DS13757 - Rev 3 page 15/24 STGAP2SICSN Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 SO-8 package information Dim. mm Min. Typ. Max. A 1.35 - 1.75 A1 0.10 - 0.25 b 0.35 - 0.49 c 0.19 - 0.25 D(1) 4.8 - 5 E1 3.8 3.9 4 E 5.8 6 6.2 e NOTES 1.27 BSC L 0.4 - 1.25 h 0.25 - 0.50 θ 0° 7° Θ1 2° 12° aaa 0.25 bbb 0.25 ccc 0.1 1. Dimension “D” does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. DS13757 - Rev 3 page 16/24 STGAP2SICSN SO-8 package information Figure 14. SO-8 mechanical data DS13757 - Rev 3 page 17/24 STGAP2SICSN SO-8 Suggested land pattern 9.2 SO-8 Suggested land pattern Figure 15. SO-8 suggested land pattern 0.6 (x8) 1.27 3.9 6.7 DS13757 - Rev 3 page 18/24 STGAP2SICSN Ordering information 10 Ordering information Table 10. Device summary DS13757 - Rev 3 Order code Output configuration Package Package marking Packaging STGAP2SiCSNTR GON-GOFF SO-8 GAP2ISN Tape and Reel STGAP2SiCSNCTR GOUT-CLAMP SO-8 GAP2ISCN Tape and Reel page 19/24 STGAP2SICSN Revision history Table 11. Document revision history DS13757 - Rev 3 Date Version Changes 13-Aug-2021 1 Initial release. 19-Oct-2021 2 Updated test condition in Table 5; updated order codes. 29-Sep-2022 3 Added UL file certification page 20/24 STGAP2SICSN Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Power-up, power-down and ‘safe state’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Control inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Miller Clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.6 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.7 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 7 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 7.1 Layout guidelines and considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 10 9.1 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 SO-8 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 DS13757 - Rev 3 page 21/24 STGAP2SICSN List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics (TJ = 25°C, VH = 18 V, VDD = 5 V unless otherwise specified) Isolation related package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UL 1577 Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs truth table (applicable when device is not in UVLO or "safe state") . . . . . . . . . . Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS13757 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 5 . 5 . 5 . 6 . 7 . 8 . 8 10 19 20 page 22/24 STGAP2SICSN List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. DS13757 - Rev 3 Block diagram - Single output and Miller Clamp configuration . . . . . . . . . . Block diagram - Separate outputs configuration . . . . . . . . . . . . . . . . . . . Pin connection (top view), Separated outputs option . . . . . . . . . . . . . . . . Pin connection (top view), Single output and Miller CLAMP option. . . . . . . Power supply configuration for unipolar and bipolar gate driving . . . . . . . . Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application diagram - Separated outputs . . . . . . . . . . . . . . . . . . . Typical application diagram - Separated outputs and negative gate driving . Typical application diagram - Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . Typical application diagram - Miller Clamp and negative gate driving . . . . . Half-bridge suggested PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 3 . 4 . 4 . 9 11 12 12 13 13 14 15 15 17 18 page 23/24 STGAP2SICSN IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS13757 - Rev 3 page 24/24