STGAP2SMTR

STGAP2S Datasheet Galvanically isolated 4 A single gate driver Features • • • • • • • • • • • • • High voltage rail up to 1700 V Driver current capability: 4 A sink/source @25°C dV/dt transient immunity ±100 V/ns in full temperature range Overall input-output propagation delay: 75 ns Separate sink and source option for easy gate driving configuration 4 A Miller CLAMP dedicated pin option UVLO function Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shut-down protection Standby function Narrow body SO8 UL 1577 recognized Application Product status link STGAP2S Product label • • • • • • • • • Motor driver for home appliances, factory automation, industrial drives and fans. 600/1200 V inverters Battery chargers Induction heating Welding UPS Power supply units DC-DC converters Power Factor Correction Description The STGAP2S is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates UVLO and thermal shutdown protection functions to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid crossconduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption. DS12541 - Rev 3 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com STGAP2S Block diagram 1 Block diagram Figure 1. Block diagram - separated outputs option VH VDD IN+ IN- Control Logic I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GON GOFF GNDISO Floating ground Figure 2. Block diagram - single output and Miller clamp option VH VDD IN+ IN- GND DS12541 - Rev 3 Control Logic I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GNDISO Floating ground A + VCLAMPth page 2/23 STGAP2S Pin description and connection diagram 2 Pin description and connection diagram Figure 3. Pin connection (top view), separated outputs option VDD 1 8 GNDISO IN+ 2 7 GOFF IN- 3 6 GON GND 4 5 VH Figure 4. Pin connection (top view), single output and Miller clamp option VDD 1 8 GNDISO IN+ 2 7 CLAMP IN- 3 6 GOUT GND 4 5 VH Table 1. Pin description Pin no. DS12541 - Rev 3 Pin name Type 1 VDD Power supply 2 2 IN+ Logic input Driver logic input, active high. 3 3 IN- Logic input Driver logic input, active low 4 4 GND Power supply Driver logic ground. 5 5 VH Power supply Gate driving positive voltage supply. - 6 GOUT Analog output Sink/source output. - 7 CLAMP Analog output Active Miller clamp. 6 - GON Analog output Source output. 7 - GOFF Analog output Sink output. 8 8 GNDISO Power supply Gate driving Isolated ground. Figure 3 Figure 4 1 Function Driver logic supply voltage. page 3/23 STGAP2S Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Test condition Min. Max. Uni t Logic supply voltage vs. GND - -0.3 6.5 V Logic pins voltage vs. GND - -0.3 6.5 V Positive supply voltage (VH vs. GNDISO) - -0.3 28 V Voltage ongate driver outputs (GON, GOFF, CLAMP vs. GNDISO) - - 0.3 VH +0.3 V DC or peak -1700 +1700 V Symbol VDD VLOGIC VH VOUT VISO-OP 3.2 Parameter Input to output isolation voltage (GND vs. GNDISO) TJ Junction temperature - -40 150 °C TS Storage temperature - -50 150 °C PDin Power dissipation input chip TA = 25 °C - 21 mW PDout Power dissipation output chip TA = 25 °C - 850 mW ESD HBM (human body model) - 2 kV Thermal data Table 3. Thermal data Symbol Rth(JA) 3.3 Parameter Thermal resistance junction to ambient Package Value Unit SO-8 123 °C/W Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Test conditions Min. Max. Unit VDD Logic supply voltage vs. GND - 3.1 5.5 V VLOGIC Logic pins voltage vs. GND - 0 5.5 V VH Positive supply voltage (VH vs. GNDISO) - 9.6 26 V FSW Maximum switching frequency(1) - - 1 MHz tOUT Output pulse width (GOUT, GON-GOFF) - 100 - ns TJ Operating junction temperature - -40 125 °C 1. Actual limit depends on power dissipation and TJ. DS12541 - Rev 3 page 4/23 STGAP2S Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics (TJ = 25 °C, VH = 15 V, VDD = 5 V, unless otherwise specified) Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics tDon IN+, IN- Input to output propagation delay ON - 50 75 90 ns tDoff IN+, IN- Input to output propagation delay OFF - 50 75 90 ns tr - Rise time CL =4.7 nF, 10% ÷ 90% - 30 - ns tf - Fall time CL =4.7 nF, 90% ÷ 10% - 30 - ns PWD - Pulse width distortion |tDon -tDoff| - - - 20 ns Inputs deglitch filter - - 20 40 ns VCM = 1500 V, see Figure 13 100 - - V/ns tdeglitch IN+, IN- CMTI(1) - Common-mode transient immunity, |dVISO/dt| VHon - VH UVLO turn-on threshold - 8.6 9.1 9.6 V VHoff - VH UVLO turn-off threshold - 7.9 8.4 8.9 V VHhyst - VH UVLO hysteresis - 0.60 0.75 0.95 V IQHU - VH undervoltage quiescent supply current VH =7 V - 1.3 1.8 mA IQH - VH quiescent supply current - - 1.3 1.8 mA IQHSBY - Standby VH quiescent supply current Standby mode - 400 550 µA SafeClp - GOFF active clamp IGOFF =0.2 A; VH floating - 2 2.3 V IQDD - VDD quiescent supply current - - 1 1.3 mA IQDDSBY - Standby VDD quiescent supply current Standby mode - 40 65 µA Vil IN+, IN- Low level logic threshold voltage - 0.29 ·VDD 1/3 · VDD 0.37 · VDD V Vih IN+, IN- High level logic threshold voltage - 0.62 ·VDD 2/3 · VDD 0.70 · VDD V IINh IN+, IN- INx logic “1” input bias current INx = 5 V IINl IN+, IN- INx logic “0” input bias current INx = GND Rpd IN+, IN- Inputs pull-down resistors Supply voltage Logic inputs 33 50 77 µA - - 1 µA INx = 5 V 65 100 150 kΩ TJ =25 °C - 4 - TJ =-40 ÷ +125 °C(1) 3 - 5 VH -0.15 VH -0.125 - Driver buffer section DS12541 - Rev 3 IGON - Source short-circuit current VGONH - Source output high level voltage IGON =100 mA A V page 5/23 STGAP2S Electrical characteristics Symbol Pin Parameter Test conditions Min. Typ. Max. Unit IGON =100 mA - 1.125 1.5 Ω TJ =25 °C - 4 - TJ =-40 ÷ +125 °C(1) 3 - 5 RGON - Source RDS_ON IGOFF - Sink short-circuit current VGOFFL - Sink output low level voltage IGOFF =100 mA - 96 120 mV RGOFF - Sink RDS_ON IGOFF =100 mA - 0.96 1.2 Ω 1.3 2 2.6 V A A Miller Clampfunction (STGAP2SC only) VCLAMPth - ICLAMP - CLAMP voltage threshold VCLAMP vs. GNDISO CLAMP short-circuit current VCLAMP =15 V TJ =25 °C - 4 - TJ =-40 ÷ +125 °C(1) 2 - 5 - VCLAMP_L - CLAMP low level output voltage ICLAMP =100 mA - 96 115 mV RCLAMP - CLAMP RDS_ON ICLAMP =100 mA - 0.96 1.15 Ω Overtemperature protection TSD - Shutdown temperature - 170 - - °C Thys - Temperature hysteresis - - 20 - °C tSTBY - Standby time See Section 5.3 200 280 500 µs tWUP - Wake-up time See Section 5.3 10 20 35 µs tawake - Wake-up delay See Section 5.3 90 140 200 µs tstbyfilt - Standby filter See Section 5.3 200 280 800 ns Standby 1. Characterization data, not tested in production. Table 6. Isolation related package specifications Parameter Clearance (Minimum External Air Gap ) Creepage (*) (Minimum External Tracking) Comparative Tracking Index (Tracking Resistance) Isolation Group DS12541 - Rev 3 Symbol Value Unit CLR 4 mm Measured from input terminals to output terminals, shortest distance through air CPG 4 mm Measured from input terminals to output terminals, shortest distance path along body CTI ≥ 400 V II Conditions DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) page 6/23 STGAP2S Electrical characteristics Table 7. Isolation characteristics Parameter Symbol Test conditions Characteristic Unit 2720 VPEAK 3200 VPEAK Method a, Type test VPR = 2720, tm = 10 s Input to Output test voltage VPR In accordance with VDE 0884-11 Partial discharge < 5 pC Method b1, 100 % Production test VPR = 3200, tm = 1 s Partial discharge < 5 pC Transient Overvoltage (Highest Allowable Overvoltage) Maximum Surge Test Voltage VIOTM tini = 60 s, Type test 4800 VPEAK VIOSM Type test 4800 VPEAK VIO = 500 V, Type test >109 Ω RIO Isolation Resistance Table 8. UL 1577 isolation voltage ratings Description Isolation Withstand Voltage, 1 min (Type test) Isolation Voltage, 1 sec (100% production) Symbol Characteristic Unit VISO 2828/4000 Vrms/ PEAK VISOtest 3394/4800 Vrms/ PEAK Recognized under the UL 1577 Component Recognition Program - file number E362869. DS12541 - Rev 3 page 7/23 STGAP2S Functional description 5 Functional description 5.1 Gate driving power supply and UVLO The STGAP2S is a flexible and compact gate driver with 4 A output current and rail-to-rail outputs. The device allows implementation of either unipolar or bipolar gate driving. Figure 5. Power supply configuration for unipolar and bipolar gate driving Unipolar gate driving VDD Bipolar gate driving VDD VDD VDD 1uF 100nF 1uF VH IN+ IN- GND I S O L A T I O N 100nF 1uF + VH 100nF VH IN+ GON GOFF GNDISO IN- GND I S O L A T I O N 100nF 1uF + VH GON GOFF 1uF + VL GNDISO Undervoltage protection is available on VH supply pin. A fixed hysteresis sets the turn-off threshold, thus avoiding intermittent operation. When VH voltage goes below the VHoff threshold, the output buffer goes in “safe state”. When VH voltage reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input pins status. The VDD and VH supply pins must be properly filtered with local bypass capacitors. The use of capacitors with different values in parallel provides both local storage for impulsive current supply and high-frequency filtering. The best filtering is obtained by using low-ESR SMT ceramic capacitors, which are therefore recommended. A 100 nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor with value in the range between 1 µF and 10 µF should be placed close to it. 5.2 Power up, power down and 'safe state' The following conditions define the “safe state”: • GOFF = ON state • GON = high impedance • CLAMP = ON state (for STGAP2SC) Such conditions are maintained at power up of the isolated side (VH < VHon) and during whole device power down phase (VH < VHoff), regardless of the value of the input pins. The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH positive supply pin is floating or not supplied the GOFF pin is therefore clamped to a voltage smaller than SafeClp. If the supply voltage VDD of the control section of the device is not supplied, the output is put in safestate, and remains in such condition until the VDD voltage returns within operative conditions. After power-up of both isolated and low voltage side the device output state depends on the input pins' status. DS12541 - Rev 3 page 8/23 STGAP2S Control inputs 5.3 Control inputs The device is controlled through the IN+ and IN- logic inputs, in accordance to the truth table described in Table 9. Table 9. Inputs truth table (applicable when device is not in UVLO or “safe state”) Input pins Output pins IN+ IN- GON GOFF L L OFF ON H L ON OFF L H OFF ON H H OFF ON Adeglitch filter allow the input pins to ignore signals with duration shorter than tdeglitch, so preventing noise spikes possibly present in the application from generating unwanted commutations. 5.4 Miller clamp function The Miller clamp function allows the control of the Miller current during the power stage switching in half-bridge configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the CGD capacitance. During the turn-off period the gate of the external switch is monitored through the CLAMP pin. The CLAMP switch is activated when gate voltage goes below the voltage threshold. VCLAMPth, thus creating a low impedance path between the switch gate and the GNDISO pin. 5.5 Watchdog The isolated HV side has a watchdog function in order to identify when it is not able to communicate with LV side, for example because the VDD of the LV side is not supplied. In this case the output of the driver is forced in “safe state” until communication link is properly established again. 5.6 Thermal shutdown protection The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature threshold, the device is forced in “safe state”. The device operation is restored as soon as the junction temperature is lower than TSD - Thys. DS12541 - Rev 3 page 9/23 STGAP2S Standby function 5.7 Standby function Inorder to reduce the power consumption of both control interface and gate driving sides the device can be put in standby mode. In standby mode the quiescent current from VDD and VH supply pins is reduced to IQDDSBY and IQHSBY respectively, and the output remains in 'safe state' (the output is actively forced low). The way to enter standby is to keep both IN+ and IN- high (“standby” value) for a time longer than tSTBY. During standby the inputs can change from the “stand-by” value. To exit stand-by, IN+ and IN- must be put in any combination different from the “standby” value for a time longer than tstbyfilt , and then in the “standby” value for a time t such that tWUP tstbyfilt t < tWUP t > tSTBY duration too short duration too long “stand-by” “stand-by” tWUP < t < tSTBY t = tawake “stand-by” Device status ACTIVE STAND-BY ACTIVE Output ACTIVE SAFE-STATE ACTIVE page 10/23 STGAP2S Typical application diagram 6 Typical application diagram Figure 7. Typical application diagram - separated outputs VDD HV_BUS VDD VH_HS UVLO VDD IN+ R C IN- VDD R Control Logic C GND HIN MCU VH I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GON GOFF GND_HS Floating ground GNDISO VDD LIN Load_ Phase VDD VH_LS VH UVLO VDD IN+ R C INR Control Logic C GND I S O L A T I O N UVLO VH Floating Section Control Logic Level Shifter GON GOFF GND_LS GNDISO Floating ground GND_PWR Figure 8. Typical application diagram - separated outputs and negative gate driving VDD HV_BUS VDD VH_HS UVLO VDD IN+ R C IN- VDD R Control Logic C GND VH I S O L A T I O N + UVLO VH VH Floating Section Control Logic Level Shifter GON GOFF VL_HS Floating ground GND_HS GNDISO VL HIN MCU + VDD LIN Load_ Phase VDD VH VH_LS UVLO VDD IN+ R C INR C GND Control Logic I S O L A T I O N + UVLO VH VH Floating Section Control Logic Level Shifter GON GOFF VL_LS Floating ground GNDISO VL DS12541 - Rev 3 + GND_LS GND_PWR page 11/23 STGAP2S Typical application diagram Figure 9. Typical application diagram - Miller clamp VDD VH_HS HV_BUS VDD VH IN+ R C IN- VDD R Control Logic C I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GND_HS Floating ground A GNDISO + VCLAMPth HIN MCU VDD LIN Load_ Phase VH_LS VDD VH IN+ R C INR Control Logic C I S O L A T I O N GND UVLO VH Floating Section Control Logic Level Shifter GOUT CLAMP GND_LS Floating ground A GNDISO + GND_PWR VCLAMPth Figure 10. Typical application diagram - Miller clamp and negative gate driving VDD HV_BUS VDD VH_HS VH IN+ R C IN- VDD R Control Logic C I S O L A T I O N GND UVLO VH + Floating Section Control Logic VH GOUT Level Shifter CLAMP VL_HS Floating ground A GND_HS GNDISO + VCLAMPth HIN MCU VL + VDD LIN Load_ Phase VDD VH_LS VH IN+ R C INR C GND Control Logic I S O L A T I O N UVLO VH + Floating Section Control Logic Level Shifter CLAMP VL_LS Floating ground A GNDISO + VCLAMPth DS12541 - Rev 3 VH GOUT VL + GND_LS GND_PWR page 12/23 STGAP2S Layout 7 Layout 7.1 Layout guidelines and considerations Inorder to optimize the PCB layout, following considerations should be taken into account: • SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF should also be placed close to the supply pins. • As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (IN+, IN-), in particular for fast switching or noisy applications. • The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop area and inductance that might bring to noise or ringing. • To avoid degradation of the isolation between the primary and secondary side of the driver, there should not be any trace or conductive area below the driver. • If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity. 7.2 Layout example Anexample of STGAP2SC Half-Bridge PCB layout with main signals highlighted by different colors is shown in Figure 11 . It is recommended to follow this example for proper positioning and connection of filtering capacitors. Figure 11. Layer traces and copper CVH1 RIN CIN CVH2 Q1 DBOOT U1 RON CG DOFF CIN RIN CVDD1 G1 ROFF RBOOT S1 G2 Q2 ROFF RIN CIN DOFF CIN U2 CVH2 TOP DS12541 - Rev 3 CG CVH1 RIN CVDD1 D1 D2 RON S2 BOTTOM page 13/23 STGAP2S Testing and characterization information 8 Testing and characterization information Figure 12. Timings definition IN+ 50% 50% IN- 50% tr tf 90% GON-GOFF 50% tr 90% 10% 10% t Doff t Don tf 90% 90% 10% 10% t Doff t Don Figure 13. CMTI test circuit VDD + VDD + S1 VH IN+ - IN- I S O L A T I O N GND GON Output V out monitoring node + VH GOFF GNDISO G1 DS12541 - Rev 3 page 14/23 STGAP2S Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 SO-8 package information Figure 14. SO-8 package outline DS12541 - Rev 3 page 15/23 STGAP2S SO-8 package information Table 10. SO-8 package mechanical data Dim. mm Min. Max. A 1.35 1.75 A1 0.1 0.25 b 0.35 0.49 c 0.19 0.25 D 4.8 5 E1 3.8 3.9 4 E 5.8 6 6.2 e DS12541 - Rev 3 Typ. Notes 1.27 BSC L 0.4 1.25 h 0.25 0.5 Ɵ 0 7 Ɵ1 2 12 aaa 0.25 bbb 0.25 ccc 0.1 page 16/23 STGAP2S Suggested land pattern 10 Suggested land pattern Figure 15. SO-8 suggested land pattern 0.6 (x8) 1.27 3.9 6.7 DS12541 - Rev 3 page 17/23 STGAP2S Ordering information 11 Ordering information Table 11. Device summary DS12541 - Rev 3 Order code Output configuration Package marking Package Packaging STGAP2SM GON-GOFF GAP2S2 SO-8 Tube STGAP2SMTR GON-GOFF GAP2S2 SO-8 Tape and reel STGAP2SCM GOUT-CLAMP GAP2SC2 SO-8 Tube STGAP2SCMTR GOUT-CLAMP GAP2SC2 SO-8 Tape and reel page 18/23 STGAP2S Revision history Table 12. Document revision history DS12541 - Rev 3 Date Version 06-Jun-2018 1 16-Jul-2021 2 25-Jul-2022 3 Changes Initial release. Updated Table 4, Table 5, Table 10 and Section 7 Added Table 6, Table 7 and Table 8 Updated Section 3.1 Absolute maximum ratings, added UL file certification page 19/23 STGAP2S Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Power up, power down and 'safe state' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Control inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Miller clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.6 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.7 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 7.1 Layout guidelines and considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 9.1 [Package name] package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 DS12541 - Rev 3 page 20/23 STGAP2S List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation related package specifications . . . . . . . . . . . . . . . . . . . . . . . Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UL 1577 isolation voltage ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs truth table (applicable when device is not in UVLO or “safe state”) SO-8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12541 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 4 . 4 . 5 . 6 . 7 . 7 . 9 16 18 19 page 21/23 STGAP2S List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. DS12541 - Rev 3 Block diagram - separated outputs option. . . . . . . . . . . . . . . . . . . . . . . Block diagram - single output and Miller clamp option . . . . . . . . . . . . . . Pin connection (top view), separated outputs option . . . . . . . . . . . . . . . Pin connection (top view), single output and Miller clamp option . . . . . . . Power supply configuration for unipolar and bipolar gate driving . . . . . . . Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application diagram - separated outputs . . . . . . . . . . . . . . . . . . Typical application diagram - separated outputs and negative gate driving Typical application diagram - Miller clamp . . . . . . . . . . . . . . . . . . . . . . Typical application diagram - Miller clamp and negative gate driving . . . . Layer traces and copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 2 . 3 . 3 . 8 10 11 11 12 12 13 14 14 15 17 page 22/23 STGAP2S IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS12541 - Rev 3 page 23/23