STGIF7CH60TS-L

STGIF7CH60TS-L Datasheet SLLIMM - 2nd series IPM, 3-phase inverter, 10 A, 600 V, short‑circuit rugged IGBT Features • 18 17 26 1 Marking area 17 18 1 26 SDIP2F-26L type L • • • • • • • • • • • • • • • IPM 10 A, 600 V, 3-phase IGBT inverter bridge including 2 control ICs for gate driving and freewheeling diodes 3.3 V, 5 V TTL/CMOS inputs with hysteresis Internal bootstrap diode Undervoltage lockout of gate drivers Smart shutdown function Short-circuit protection Shutdown input/fault output Separate open emitter outputs Built-in temperature sensor Comparator for fault protection Short-circuit rugged TFS IGBT Very fast, soft recovery diodes 85 kΩ NTC, UL 1434, CA 4 recognized Fully isolated package Isolation ratings of 1600 Vrms/min. UL recognition: UL 1557, file E81734 Applications • • • • • Product status link STGIF7CH60TS-L Product summary Order code STGIF7CH60TS-L Marking GIF7CH60TS-L Package SDIP2F-26L type L Packing Tube 3-phase inverters for motor drives Washing machines Dryer Industrial fans Pumps Description This second series of SLLIMM (small low-loss intelligent molded module) provides a compact, high-performance AC motor drive in a simple, rugged design. It combines new ST proprietary control ICs (one LS and one HS driver) with an improved shortcircuit rugged trench gate field-stop (TFS) IGBT, making it ideal for motor drives operating up to 20 kHz in hard-switching circuitries. DS10416 - Rev 10 - June 2021 For further information contact your local STMicroelectronics sales office. www.st.com STGIF7CH60TS-L Internal schematic and pin description 1 Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram and pin configuration NC(1 ) (26)T1 VbootU(2) (25)T2 VbootV(3) VbootW(4) (24)P HinU(5) (23)U HinV(6) HinW(7) (22)V VccH(8) (21)W GND(9) H-side LinU(10) LinV(11) LinW(12) (20)NU VccL(13) (19)NV SD/OD(14) Cin(15) (18)NW GND(16) TSO(17) L-side GIPG120520140842FSR DS10416 - Rev 10 page 2/24 STGIF7CH60TS-L Internal schematic and pin description Table 1. Pin description Pin DS10416 - Rev 10 Symbol Description 1 NC 2 VBOOTu Bootstrap voltage for U phase 3 VBOOTv Bootstrap voltage for V phase 4 VBOOTw Bootstrap voltage for W phase 5 HINu High-side logic input for U phase 6 HINv High-side logic input for V phase 7 HINw High-side logic input for W phase 8 VCCH High-side low voltage power supply 9 GND Ground 10 LINu Low-side logic input for U phase 11 LINv Low-side logic input for V phase 12 LINw Low-side logic input for W phase 13 VCCL Low-side low voltage power supply 14 SD /OD 15 CIN Comparator input 16 GND Ground 17 TSO Temperature sensor output 18 NW Negative DC input for W phase 19 NV Negative DC input for V phase 20 NU Negative DC input for U phase 21 W W phase output 22 V V phase output 23 U U phase output 24 P Positive DC input 25 T2 NTC thermistor terminal 2 26 T1 NTC thermistor terminal 1 Shutdown logic input (active low) / open-drain (comparator output) page 3/24 STGIF7CH60TS-L Absolute maximum ratings 2 Absolute maximum ratings TJ = 25 °C unless otherwise noted. Table 2. Inverter parts Symbol Value Unit Supply voltage between P -NU, -NV, -NW 450 V Supply voltage (surge) between P -NU, -NV, -NW 500 V Collector-emitter voltage each IGBT 600 V Continuous collector current each IGBT (TC = 25 °C) 10 Continuous collector current each IGBT (TC = 80 °C) 7 ±ICP Peak collector current each IGBT (less than 1 ms) 20 A PTOT Total power dissipation at TC = 25 °C each IGBT 31 W 5 μs VPN VPN(surge) VCES ±IC tSCW Parameter Short-circuit withstand time, VCE = 300 V, TJ = 125 °C, VCC = Vboot = 15 V, VIN = 0 to 5 V A Table 3. Control parts Symbol Min. Max. Unit Supply voltage applied between VCCH-GND, VCCL-GND - 0.3 20 V VBOOT Bootstrap voltage - 0.3 619 V VOUT Output voltage applied between U, V, W and GND VBOOT - 21 VBOOT + 0.3 V VCIN Comparator input voltage - 0.3 20 V VIN Logic input voltage applied between HINx, LINx and GND - 0.3 15 V VSD/OD Open drain voltage -0.3 7 V ISD/OD Open drain sink current 10 mA 5.5 V 7 mA VCC Parameter VTSO Temperature sensor output voltage ITSO Temperature sensor output current -0.3 Table 4. Total system Symbol VISO DS10416 - Rev 10 Parameter Isolation withstand voltage applied between each pin and heat sink plate (AC voltage, t = 60 s) Value Unit 1600 Vrms TJ Power chip operating junction temperature range -40 to 175 °C TC Module operation case temperature range -40 to 125 °C page 4/24 STGIF7CH60TS-L Thermal data 2.1 Thermal data Table 5. Thermal data Symbol RthJC DS10416 - Rev 10 Parameter Value Thermal resistance, junction-to-case single IGBT 4.8 Thermal resistance, junction-to-case single diode 6 Unit °C/W page 5/24 STGIF7CH60TS-L Electrical characteristics 3 Electrical characteristics TJ = 25 °C unless otherwise specified. 3.1 Inverter parts Table 6. Static Symbol ICES Parameter Collector cut-off current Test conditions VCE = 600 V, VCC = Vboot = 15 V VCC = Vboot = 15 V, VIN(1) = 0 to 5 V, VCE(sat) Collector-emitter saturation voltage IC = 7 A VCC = Vboot = 15 V, VIN(1) = 0 to 5 V, Typ. - 1.5 Max. Unit 100 µA 1.95 V - 1.7 - 1.5 - 1.6 Min. Typ. Max. Turn-on time - 310 - Crossover time on - 156 - Turn-off time - 412 - - 110 - - 230 - IC = 10 A VF Min. Diode forward voltage VIN(1) = 0, IC = 7 A VIN (1) = 0, IC = 10 A 2.1 V V 1. Applied between HINx, LINx and GND for x = U, V, W. Table 7. Inductive load switching time and energy Symbol ton(1) (1) tc(on) toff(1) (1) tc(off) trr Parameter Crossover time off Reverse recovery time Test conditions VDD = 300 V, VCC = Vboot = 15 V, VIN (2) = 0 to 5 V, IC = 7 A Eon Turn-on switching energy - 197 - Eoff Turn-off switching energy - 84 - Err Reverse recovery energy - 21 - Turn-on time - 320 - Crossover time on - 172 - Turn-off time - 400 - - 102 - - 248 - ton(1) (1) tc(on) toff(1) (1) tc(off) trr Crossover time off Reverse recovery time VDD = 300 V, VCC = Vboot = 15 V, VIN (2) = 0 to 5 V, IC = 10 A Eon Turn-on switching energy - 305 - Eoff Turn-off switching energy - 120 - Err Reverse recovery energy - 26 - Unit ns µJ ns µJ 1. ton and toff include the propagation delay time of the internal drive. tc(on) and tc(off) are the switching times of the IGBT itself under the internally given gate driving conditions. 2. Applied between HINx, LINx and GND for x = U, V, W. DS10416 - Rev 10 page 6/24 STGIF7CH60TS-L Inverter parts Figure 2. Switching time test circuit Ic Vcc VCC BOOT HIN HVG GND OUT L 5V + C Vdd - 0V Input VCC LIN + SD Vce - Rsd +5V LVG CIN GND Figure 3. Switching time definition 100% IC 100% IC t rr IC VCE VIN VIN t ON VIN(ON) VCE IC t C(ON) 10% IC 90% IC 10% VCE (a) turn-on t OFF VIN(OFF) t C(OFF) 10% VCE 10% IC (b) turn-off AM09223V1 DS10416 - Rev 10 page 7/24 STGIF7CH60TS-L Control/protection parts 3.2 Control/protection parts Table 8. High- and low-side drivers Symbol Parameter Test condition Vil Low logic level voltage Vih High logic level voltage IINh IN logic “1” input bias current INx = 15 V IINl IN logic “0” input bias current INx = 0 V Min. Typ. Max. Unit 0.8 V 2 80 V 150 200 µA 1 µA High-side VCC_hys VCC UV hysteresis 1.2 1.4 1.7 V VCCH_th(on) VCCH UV turn-on threshold 11 11.5 12 V VCCH_th(off) VCCH UV turn-off threshold 9.6 10.1 10.6 V VBS UV hysteresis 0.5 1 1.6 V VBS_th(on) VBS UV turn-on threshold 10.1 11 11.9 V VBS_th(off) VBS UV turn-off threshold 9.1 10 10.9 V VBS_hys IQBSU Under voltage VBS quiescent current VBS = 9 V, HINx(1) = 5 V 55 75 µA IQBS VBS quiescent current VCC = 15 V, HINx(1) = 5 V 125 170 µA Iqccu Under voltage quiescent supply current VCC = 9 V, HINx(1) = 0 V 190 250 µA Iqcc Quiescent current VCC = 15 V, HINx(1) = 0 V 560 730 µA RDS(on) BS driver ON resistance VCC_hys VCC UV hysteresis 1.1 1.4 1.6 V VCCL_th(on) VCCL UV turn-on threshold 10.4 11.6 12.4 V VCCL_th(off) VCCL UV turn-off threshold 9.0 10.3 11 V 600 800 µA 700 900 µA 0.5 0.6 0.75 V 25 50 70 µA 1 µA 150 Ω Low-side VCC = 10 V, Iqccu Under voltage quiescent supply current SD pulled to 5 V through RSD = 10 kΩ, CIN = LINx(1) = 0 V Iqcc Quiescent current VCC = 15 V, SD= 5 V, CIN = LINx(1) = 0 V VSSD Smart SD unlatch threshold ISDh SD logic “1” input bias current SD = 5 V ISDl SD logic “0” input bias current SD = 0 V 1. Applied between HINx, LINx and GND for x = U, V, W. DS10416 - Rev 10 page 8/24 STGIF7CH60TS-L Control/protection parts Table 9. Temperature sensor output Symbol VTSO Parameter Temperature sensor output voltage ITSO_SNK Temperature sensor sink current capability ITSO_SRC Temperature sensor source current capability Test condition TJ = 25 °C Min. Typ. Max. Unit 0.974 1.16 1.345 V 0.1 mA 4 mA Table 10. Sense comparator (VCC = 15 V, unless otherwise is specified) Symbol Parameter ICIN CIN input bias current Vref Internal reference voltage VOD Open-drain low level output voltage Test condition VCIN = 1 V Min. Typ. -0.2 460 510 Iod = 5 mA Max. Unit 0.2 µA 560 mV 500 mV 410 ns SD pulled to 5 V through RSD = 10 kΩ; tCIN_SD CIN comparator delay to SD measured applying a voltage step 0-1 V to pin CIN; 240 320 50% CIN to 90% SD SD pulled to 5 V through RSD= 10 kΩ; SRSD SD fall slew rate CL= 1 nF through SD and ground; 25 V/µs 90% SD to 10% SD The comparator stays enabled even if VCC is in the UVLO condition but higher than 4 V. DS10416 - Rev 10 page 9/24 STGIF7CH60TS-L Fault management 4 Fault management The device integrates an open-drain output connected to the SD pin. As soon as a fault occurs, the open-drain is activated and the LVGx outputs are forced low. Two types of fault can be identified: • Overcurrent (OC) sensed by the internal comparator (see more detail in Section 4.1 Smart shutdown function); • Undervoltage on supply voltage (VCC) Each fault enables the SD open drain for a different time, as described in the following table. Table 11. Fault timing Symbol Parameter OC Over-current event UVLO Event time (1) SD open-drain enable time result (1)(2) ≤ 24 μs 24 μs > 24 µs OC time ≤ 70 μs 70 µs > 70 µs Under-voltage lockout event until the VCC_LS exceeds the VCC_LS UV turn ON threshold UVLO time 1. Typical value (-40 °C ≤ TJ ≤ +125 °C). 2. Without contribution of the RC network on SD. Actually, the device remains in a fault condition (SD at low logic level and LVGx outputs disabled) for a time also depending on the RC network connected to the SD pin. The network generates a time contribution that is added to the internal value. Figure 4. Overcurrent timing (without contribution of the RC network on SD) GIPG120520141638FSR DS10416 - Rev 10 page 10/24 STGIF7CH60TS-L Fault management Figure 5. UVLO timing (without contribution of the RC network on SD) GIPG120520141644FSR DS10416 - Rev 10 page 11/24 STGIF7CH60TS-L Smart shutdown function 4.1 Smart shutdown function The device integrates a comparator committed to the fault sensing function. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on the SD input. When the comparator triggers, the device is set in shutdown state and its outputs are all set to low level. Figure 6. Smart shutdown timing waveforms in case of overcurrent event comp Vref PROTECTION CIN t CIN_SD LIN LVG SD l open-drain gate (internal) t2 t1 t OC real disable time Fast shutdown: the driver outputs are set in SD state immediately after comparator triggering even if the SD signal has not yet reached the lower input threshold t1 SHUTDOWN CIRCUIT t2 where: VBIAS RSD SD FROM / TO CONTROLLER CSD R PD_SD R ON_OD SMART SD LOGIC RON_OD = VOD/5 mA, see Table 10. Sense comparator (VCC = 15 V, unless otherwise is specified); RPD_SD (typ.) = 5 V/ISDh DS10416 - Rev 10 page 12/24 STGIF7CH60TS-L Smart shutdown function In common overcurrent protection designs, the comparator output is usually connected to the SD input and an RC network is connected to this SD line in order to provide a mono-stable circuit which implements a protection time that follows the fault condition. As opposed to common fault detection systems, the device smart shutdown architecture allows the immediate turn-off of output gates driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual switching off of the outputs. In fact, the time delay between the fault and the turning off of the outputs is no longer dependent on the RC value of the external network connected to the pin. In the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time, the internal logic turns on the open-drain output and holds it on until the SD voltage goes below the VSSD threshold and the toc time is elapsed. The driver outputs restart following the input pins as soon as the voltage at the SD pin reaches the higher threshold of the SD logic input. The smart shutdown system provides the possibility to increase the time constant of the external RC network (i.e., the disable time after the fault event) up to very high values without increasing the delay time of the protection. DS10416 - Rev 10 page 13/24 STGIF7CH60TS-L Temperature monitoring solutions 5 Temperature monitoring solutions 5.1 TSO output The device integrates a temperature sensor. A voltage proportional to the die temperature is available on the TSO pin. When this function is not used, the pin can be left floating. Figure 7. VTSO output characteristics vs LVIC temperature VTSO (V) IGBT110820161234TSO 2.8 Min 2.2 1.6 Typ Max 1.0 0.4 0 5.2 25 50 75 100 T (°C) NTC thermistor Table 12. NTC thermistor Symbol DS10416 - Rev 10 Parameter Test condition Min. Typ. Max. Unit R25 Resistance T = 25 °C 85 kΩ R125 Resistance T = 125 °C 2.6 kΩ B B-constant T = 25 to 100 °C 4092 K T Operating temperature range -40 125 °C page 14/24 STGIF7CH60TS-L NTC thermistor Figure 8. NTC resistance vs temperature GIPG120520142249FSR R(kΩ) 3000 2500 2000 1500 Typ 1000 500 0 -50 Max Min -25 0 25 50 75 100 125 T(°C) Figure 9. NTC resistance vs temperature - zoom GIPG120520141304FSR R(kΩ) 30 25 20 Max 15 Typ 10 Min 5 0 50 DS10416 - Rev 10 60 70 80 90 100 110 120 T(°C) page 15/24 DS10416 - Rev 10 VTSO/NTC Fault Lin W Lin V Lin U Hin W 3.3V/5 V R1 R1 R1 R1 R1 R1 Vcc Vc c CbootW VTSO/NTC CSD RSD C1 C1 C1 C1 C1 C1 C3 CTSO - + - + C3 Cvcc Cvc c Cboot V C2 C2 C3 SGN_GND Dz2 Dz2 CbootU (17)TSO (16)GND (15)Cin (14)SD/OD (13)VccL (12)LinW (11)LinV (10)LinU (9)GND (8)VccH (7)HinW (6)HinV (5)HinU (4)VbootW (3)VbootV (2)VbootU (1)NC L-side H-side RSF CSF NW(18) NV(19) NU(20) W(21) V(22) U(23) P(24) T2(25) T1(26) PWR_GND Rshunt M CTO to MCU/op-amp RTO C4 VTSO/NTC Cvdc - + 6 Hin V Hin U Dz1 Dz1 Dz1 3.3V/5 V Application circuit example STGIF7CH60TS-L Application circuit example Figure 10. Application circuit example MICROCONTROLLER Application designers are free to use a different scheme according to the device specifications. page 16/24 STGIF7CH60TS-L Guidelines 6.1 Guidelines 1. 2. 3. 4. 5. 6. 7. 8. Input signals HIN, LIN are active-high logic. A 100 kΩ (typ.) pull-down resistor is built-in for each input pin. To prevent input signal oscillations, the wiring of each input should be as short as possible and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Besides, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to each Vcc pin and in parallel with the bypass capacitor. The use of an RC filter (RSF, CSF) prevents protection circuit malfunctions. The time constant (RSF x CSF) should be set to 1 µs and the filter must be placed as close as possible to the CIN pin. The SD is an input/output pin (open-drain type if it is used as output). It should be pulled up to a power supply (i.e., MCU bias at 3.3/5 V) by a resistor value, which can keep the Iod no higher than 5 mA (VOD ≤ 500 mV when open-drain MOSFET is ON). The filter on SD should be sized to get a desired re-starting time after a fault event and placed as close as possible to the SD pin. A decoupling capacitor CTSO between 1 nF and 10 nF can be used to increase the noise immunity of the TSO thermal sensor; a similar decoupling capacitor COT (between 10 nF and 100 nF) can be implemented if the NTC thermistor is available and used. In both cases, their effectiveness is improved if these capacitors are placed close to the MCU. The decoupling capacitor C3 (100 to 220 nF with low ESR and low ESL) in parallel with each Cboot filters high-frequency disturbances. Both Cboot and C3 (if present) should be placed as close as possible to the U,V,W and Vboot pins. Bootstrap negative electrodes should be connected to the U,V,W terminals directly and separated from the main output wires. To prevent overvoltage on the VCC pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor CVdc prevents surge destruction. Both capacitors C4 and CVdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). 9. By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible. 10. Low inductance shunt resistors should be used for phase leg current sensing. 11. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. 12. The connection of the SGN_GND to the PWR_GND at one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note. Table 13. Recommended operating conditions Symbol Test conditions VPN Supply voltage Applied between P-Nu, NV, Nw VCC Control supply voltage Applied between VCC-GND VBS High-side bias voltage tdead Blanking time to prevent arm-short For each input signal fPWM PWM input signal TC DS10416 - Rev 10 Parameter Case operation temperature Applied between VBOOTi-OUTi for i = U, V, W -40 °C < TC < 100 °C -40 °C < TJ < 125 °C Min. 13.5 13 Typ. Max. Unit 300 400 V 15 18 V 18 V 1.0 µs 20 kHz 100 °C page 17/24 STGIF7CH60TS-L Electrical characteristics (curves) 7 Electrical characteristics (curves) Figure 11. Output characteristics IC (A) IGBT130820151443OC25 VCC = 18 V Figure 12. VCE(sat) vs collector current VCE(sat) (V) IGBT130820151444VCEC VCC = 15 V 2.5 15 13 V 15 V 2.0 TJ = 175 °C 10 TJ = 25 °C 1.5 5 1.0 0 0 0.5 1.0 1.5 2.0 VCE (V) Figure 13. IC vs case temperature IC (A) GADG020420201304CCT 0.5 0 5 10 15 IC (A) Figure 14. Diode VF vs forward current VF (V) IGBT130820151446DVF VGE ≥ 15 V, 10 TJ = 25 °C TJ ≤ 175 °C 1.5 8 TJ = 175 °C 6 1.0 4 0.5 2 0 0 25 50 75 100 125 150 TC (°C) Figure 15. Eon switching energy vs collector current EON (mJ) IGBT130820151447ONSLC VDD = 300 V, VCC = Vboot = 15 V 1.2 0.0 0 5 10 15 IF (A) Figure 16. Eoff switching energy vs collector current EOFF (mJ) IGBT130820151451OFFSLC VDD = 300 V, VCC = Vboot = 15 V 0.4 1.0 0.8 0.3 TJ = 175 °C 0.6 0.2 0.4 TJ = 25 °C DS10416 - Rev 10 5 10 15 TJ = 25 °C 0.1 0.2 0.0 0 TJ = 175 °C IC (A) 0.0 0 5 10 15 IC (A) page 18/24 STGIF7CH60TS-L Electrical characteristics (curves) Figure 17. Thermal impedance K IGBT260620151422ZTH 10 -1 10 -2 10 -4 DS10416 - Rev 10 10 -3 10 -2 10 -1 10 0 t p (s) page 19/24 STGIF7CH60TS-L Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 8.1 SDIP2F-26L type L package information Figure 18. SDIP2F-26L type L package outline 8450803_5_type_L DS10416 - Rev 10 page 20/24 STGIF7CH60TS-L SDIP2F-26L type L package information Table 14. SDIP2F-26L type L package mechanical data Ref. Dimensions (mm) Min. Typ. Max. A 37.50 38.00 38.50 A1 0.97 1.22 1.47 A2 0.97 1.22 1.47 A3 34.70 35.00 35.30 c 1.45 1.50 1.55 B 23.50 24.00 24.50 B1 12.00 B2 13.90 14.40 14.90 B3 28.90 29.40 29.90 C 3.30 3.50 3.70 C1 5.00 5.50 6.00 C2 13.50 14.00 14.50 E2 DS10416 - Rev 10 1.80 e 3.356 3.556 3.756 e1 1.578 1.778 1.978 e2 7.42 7.62 7.82 e3 4.88 5.08 5.28 e4 2.34 2.54 2.74 f 0.45 0.60 0.75 f1 0.35 0.50 0.65 F 1.95 2.10 2.25 F1 0.95 1.10 1.25 R 1.55 1.575 1.60 T 0.375 0.40 0.425 V 0° 5° page 21/24 STGIF7CH60TS-L Revision history Table 15. Document revision history Date Revision Changes 20-Jun-2014 1 Initial release 27-Aug-2014 2 Updated Table 1: Device summary. 28-Apr-2015 3 Updated title, features and description in cover page. Updated Table 3: Inverter parts and Table 6: Thermal data. Text and formatting edits throughout document On cover page: - updated Features in Section 2: Absolute maximum ratings 13-Aug-2015 4 - updated Table 3, Table 4, Table 5 and Table 6 in Section 3: Electrical characteristics - updated Table 7, Table 8 and Table 9 in Section 6: Recommendations - added Table 11 Added Section 8: Electrical characteristics (curves) 03-Sep-2015 5 22-Dec-2015 6 Modified: title and Figure 6 Minor text changes Document status promoted from preliminary to production data. Minor text changes. Updated Section 8.1: "SDIP2F-26L type L package information". 27-Jul-2017 7 Updated VTSO parameter in Table 10: "Temperature sensor output" and Figure 15: "VTSO output characteristics vs LVIC temperature". Minor text changes. Removed maturity status indication from cover page. 09-Jul-2018 8 Updated Description on cover page. Updated Table 11. Fault timing. Minor text changes Updated SDIP2F-26L type L package drawing in cover page. 06-Apr-2020 9 Added Figure 13. IC vs case temperature. Updated Package information. Minor text changes. Updated Features in cover page. 01-Jun-2021 10 Updated Table 4. Total system. Minor text changes. DS10416 - Rev 10 page 22/24 STGIF7CH60TS-L Contents Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 3 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Inverter parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Control/protection parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 5 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Temperature monitoring solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.1 TSO output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.1 SDIP2F-26L type L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 DS10416 - Rev 10 page 23/24 STGIF7CH60TS-L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS10416 - Rev 10 page 24/24