STGIPN3H60-E

STGIPN3H60-E SLLIMM™-nano (small low-loss intelligent molded module) IPM, 3 A - 600 V 3-phase IGBT inverter bridge Datasheet - preliminary data Applications • 3-phase inverters for motor drives • Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps Description NDIP-26L Features • IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes • Optimized for low electromagnetic interference • VCE(sat) negative temperature coefficient • 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors This intelligent power module implements a compact, high performance AC motor drive in a simple, rugged design. It is composed of six IGBTs with freewheeling diodes and three halfbridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics. • Undervoltage lockout • Internal bootstrap diode • Interlocking function • Smart shutdown function • Comparator for fault protection against overtemperature and overcurrent • Op amp for advanced current sensing • Optimized pinout for easy board layout • ESD voltage (HBM C=100 pF, R=1.5 kȍ) up to ±2 kV Table 1. Device summary Order code Marking Package Packaging STGIPN3H60-E GIPN3H60-E NDIP-26L Tube December 2014 DocID027271 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/22 www.st.com Contents STGIPN3H60-E Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 DocID027271 Rev 1 STGIPN3H60-E 1 Internal schematic diagram and pin configuration Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram PIN 1 PIN 26 GND NW GND SD-OD HVG Vcc W VCC HIN W HIN OUT W, OUT W LVG SD-OD LIN W VBOOT LIN Vboot W OP+ GND OPOUT OPVcc V OP+ OPOUT OP- HVG VCC OUT NV V, OUT V LVG HIN V HIN SD-OD LIN V VBOOT LIN Vboot V CIN GND CIN NU HVG Vcc U VCC OUT U,OUT U LVG HIN U SD-OD LIN U P HIN SD-OD VBOOT LIN Vboot U PIN 16 PIN 17 AM09916v1 DocID027271 Rev 1 3/22 22 Internal schematic diagram and pin configuration STGIPN3H60-E Table 2. Pin description 4/22 Pin Symbol Description 1 GND 2 SD / OD 3 VCC W Low voltage power supply W phase 4 HIN W High side logic input for W phase 5 LIN W Low side logic input for W phase 6 OP+ 7 OPOUT 8 OP- 9 VCC V Low voltage power supply V phase 10 HIN V High side logic input for V phase 11 LIN V Low side logic input for V phase 12 CIN 13 VCC U Low voltage power supply for U phase 14 HIN U High side logic input for U phase 15 SD / OD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Ground Shut down logic input (active low) / open drain (comparator output) Op amp non inverting input Op amp output Op amp inverting input Comparator input Shut down logic input (active low) / open drain (comparator output) Low side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output Negative DC input for W phase DocID027271 Rev 1 STGIPN3H60-E Internal schematic diagram and pin configuration Figure 2. Pin layout (top view) (*) Dummy pin internally connected to P (positive DC input). DocID027271 Rev 1 5/22 22 Electrical ratings STGIPN3H60-E 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol Parameter Value Unit 600 V VCES Each IGBT collector emitter voltage (VIN(1) = 0) ± IC (2) Each IGBT continuous collector current at TC = 25°C 3 A ± ICP (3) Each IGBT pulsed collector current 18 A Each IGBT total dissipation at TC = 25°C 8 W PTOT 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: Tj ( max ) – TC IC ( T C ) = ------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 3. Pulse width limited by max junction temperature Table 4. Control part Symbol Parameter Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied between OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC +0.3 V Vop+ OPAMP non-inverting input - 0.3 VCC +0.3 V Vop- OPAMP inverting input - 0.3 VCC +0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied between HIN, LIN and GND - 0.3 15 V Open drain voltage - 0.3 15 V 50 V/ns VIN VSD/OD ΔVOUT/dT Allowed output slew rate Table 5. Total system Symbol VISO 6/22 Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 sec.) Value Unit 1000 V Tj Power chips operating junction temperature -40 to 150 °C TC Module case operation temperature -40 to 125 °C DocID027271 Rev 1 STGIPN3H60-E 2.2 Electrical ratings Thermal data Table 6. Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient DocID027271 Rev 1 Value Unit 50 °C/W 7/22 22 Electrical characteristics 3 STGIPN3H60-E Electrical characteristics TJ = 25 °C unless otherwise specified. Table 7. Inverter part Symbol VCE(sat) ICES VF Parameter Test conditions Min. Typ. Max. VCC = Vboot = 15 V, VIN(1)= 0 - 5 V, IC = 1 A - 2.15 2.6 VCC = Vboot = 15 V, VIN(1)= 0 - 5 V, IC = 1 A, TJ = 125 °C - 1.65 Collector-cut off current (VIN(1)= 0 “logic state”) VCE = 550 V, VCC = VBoot = 15 V - 250 μA Diode forward voltage VIN(1) = 0 “logic state”, IC = 1 A - 1.7 V Collector-emitter saturation voltage Unit V Inductive load switching time and energy ton tc(on) toff tc(off) trr Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching losses Eoff Turn-off switching losses VDD = 300 V, VCC = Vboot = 15 V, VIN(1) = 0 - 5 V, IC = 1 A (see Figure 4) - 275 - 90 - 890 - 125 - 50 - 18 - 13 ns μJ 1. Applied between HINi, LINi and GND for i = U, V, W (LIN inputs are active-low). Note: 8/22 tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. DocID027271 Rev 1 STGIPN3H60-E Electrical characteristics Figure 3. Switching time test circuit INPUT BOOT /Lin HVG /SD RSD Hin VCC BUS VBOOT>VCC +5V L OUT Vcc IC DT LVG GND CP+ VCE 0 1 Figure 4. Switching time definition 100% IC 100% IC t rr IC VCE VCE IC VIN VIN t ON t OFF t C(OFF) t C(ON) VIN(ON) 10% IC 90% IC 10% VCE (a) turn-on Note: VIN(OFF) 10% VCE (b) turn-off 10% IC AM09223V1 Figure 4 “Switching time definition” refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. DocID027271 Rev 1 9/22 22 Electrical characteristics 3.1 STGIPN3H60-E Control part Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn OFF threshold 10 10.5 11 V VCC_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 150 μA Iqcc Quiescent current Vcc = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 1 mA Vref Internal comparator (CIN) reference voltage 0.58 V 0.5 0.54 Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current VBS < 9 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 70 110 μA IQBS VBS quiescent current VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 200 300 μA Bootstrap driver on resistance LVG ON 120 VBS_hys RDS(on) ȍ Table 10. Logic inputs (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Vil Low logic level voltage 0.8 1.1 V Vih High logic level voltage 1.9 2.25 V 260 μA 1 μA 20 μA 1 μA 300 μA IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V 10/22 DocID027271 Rev 1 110 3 30 175 6 120 STGIPN3H60-E Electrical characteristics Table 10. Logic inputs (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions ISDl SD logic “1” input bias current SD = 0 V Dt Dead time see Figure 5 Min. Typ. Max. Unit 3 μA 180 ns Table 11. OPAMP characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Input bias current (1) Test condition Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Vicm Input common mode voltage range VOL Low level output voltage RL = 10 kW to VCC VOH High level output voltage RL = 10 kW to GND 14 14.7 V Source, Vid = +1; Vo = 0 V 16 30 mA Sink, Vid = -1; Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/μs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kW 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Output short-circuit current Io SR 0 V 75 150 mV 1. The direction of input current is out of the IC. Table 12. Sense comparator characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Iib Input bias current VCIN = 1 V 3 μA Vol Open drain low level output voltage Iod = 3 mA 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor 90 130 ns SR Slew rate CL = 180 pF; Rpu = 5 kΩ 60 tsd Shutdown to high / low side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V tisd Comparator triggering to high / low side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CIN td_comp DocID027271 Rev 1 50 125 V/μsec 200 ns 50 200 250 11/22 22 Electrical characteristics STGIPN3H60-E Table 13. Truth table Logic input (VI) Output Condition SD/OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X X L L Interlocking half-bridge tri-state H L H L L 0 “logic state” half-bridge tri-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: 12/22 X: don’t care DocID027271 Rev 1 STGIPN3H60-E Waveform definitions Figure 5. Dead time and interlocking waveform definitions HIN INTE RLO CK ING CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN INTE RLO CK 3.2 Electrical characteristics LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected together and driven by just one control signal DocID027271 Rev 1 13/22 22 Smart shutdown function 4 STGIPN3H60-E Smart shutdown function The STGIPN3H60-E integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple overcurrent protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the half bridge in 3-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. 14/22 DocID027271 Rev 1 STGIPN3H60-E Smart shutdown function Figure 6. Smart shutdown timing waveforms comp Vref CP+ HIN/LIN PROTECTION HVG/LVG SD/OD open drain gate (internal) disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold An approximation of the disable time is given by: SHUT DOWN CIRCUIT VBIAS where: RSD SD/OD FROM/TO CONTROLLER CSD RON_OD SMART SD LOGIC RPD_SD AM12947v1 Please refer to Table 12 for internal propagation delay time details. DocID027271 Rev 1 15/22 22 Application information 5 STGIPN3H60-E Application information Figure 7. Typical application circuit 16/22 DocID027271 Rev 1 STGIPN3H60-E 5.1 Application information Recommendations • Input signal HIN is active high logic. An 85 kΩ (typ.) pull-down resistor is built-in for each high side input. If an external RC filter is used for noise immunity, attention should be given to the variation of the input signal level. • Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. • To prevent input signal oscillation, the wiring of each input should be as short as possible. • By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-coupler is possible. • Each capacitor should be located as close as possible to the pins of the IPM. • Low inductance shunt resistors should be used for phase leg current sensing. • Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitors mounted close to the module pins will further improve performance. • The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Table 14. Recommended operating conditions Symbol Test conditions Min. VPN Supply voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCCGND VBS High side bias voltage Applied between VBOOTiOUTi for i = U, V, W 13 tdead Blanking time to prevent Arm-short For each input signal 1.5 fPWM PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C TC Note: Parameter Case operation temperature 13.5 Typ. Max. Unit 300 500 V 15 18 V 18 V μs 25 kHz 100 °C For further details refer to AN4043. DocID027271 Rev 1 17/22 22 Package mechanical data 6 STGIPN3H60-E Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. NDIP-26L type C mechanical drawing B% 18/22 DocID027271 Rev 1 STGIPN3H60-E Package mechanical data Table 15. NDIP-26L type C mechanical data mm Dim. Min. Typ. A Max. 4.40 A1 0.80 1.00 1.20 A2 3.00 3.10 3.20 A3 1.70 1.80 1.90 A4 5.70 5.90 6.10 b 0.53 b1 0.52 b2 0.83 b3 0.82 c 0.46 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.50 0.77 1.00 D2 0.35 0.53 0.70 0.72 0.60 0.68 1.02 0.90 0.98 0.59 D3 29.55 E 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eB1 16.10 16.40 16.70 eB2 21.18 21.48 21.78 L 1.24 1.39 1.54 DocID027271 Rev 1 19/22 22 Package mechanical data STGIPN3H60-E AN T IS T AT IC S 03 P VC AM10474v1 Figure 9. NDIP-26L tube dimensions (dimensions are in mm.) 8313150_A Note: 20/22 Base quantity 17 pcs, bulk quantity 476 pcs. DocID027271 Rev 1 STGIPN3H60-E 7 Revision history Revision history Table 16. Document revision history Date Revision 05-Dec-2014 1 Changes Initial release. DocID027271 Rev 1 21/22 22 STGIPN3H60-E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 22/22 DocID027271 Rev 1