STGIPN3H60-H

STGIPN3H60-H SLLIMM™-nano small low-loss intelligent molded module IPM, 3 A, 600 V, 3-phase IGBT inverter bridge Datasheet - production data Applications   3-phase inverters for motor drives Dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps Description Features            IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes Optimized for low electromagnetic interference VCE(sat) negative temperature coefficient 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down/pull up resistors Undervoltage lockout Internal bootstrap diode Interlocking function Smart shutdown function Comparator for fault protection against overtemperature and overcurrent Op amp for advanced current sensing Optimized pinout for easy board layout This intelligent power module implements a compact, high performance AC motor drive in a simple, rugged design. It is composed of six IGBTs with freewheeling diodes and three halfbridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics. Table 1: Device summary Order code Marking Package Packing STGIPN3H60-H GIPN3H60-H NDIP-26L Tube September 2016 DocID024132 Rev 4 This is information on a product in full production. 1/23 www.st.com Contents STGIPN3H60-H Contents 1 Internal schematic diagram and pin configuration ....................... 3 2 Electrical ratings ............................................................................. 6 3 2.1 Absolute maximum ratings ................................................................ 6 2.2 Thermal data ..................................................................................... 7 Electrical characteristics ................................................................ 8 3.1 Inverter part ....................................................................................... 8 3.2 Control part ..................................................................................... 10 3.3 Waveform definitions....................................................................... 13 4 Smart shutdown function ............................................................. 14 5 Application circuit example .......................................................... 16 5.1 6 7 2/23 Guidelines ....................................................................................... 17 Package information ..................................................................... 18 6.1 NDIP-26L type C package information ............................................ 19 6.2 NDIP-26L packing information ........................................................ 21 Revision history ............................................................................ 22 DocID024132 Rev 4 STGIPN3H60-H 1 Internal schematic diagram and pin configuration Internal schematic diagram and pin configuration Figure 1: Internal schematic diagram DocID024132 Rev 4 3/23 Internal schematic diagram and pin configuration STGIPN3H60-H Table 2: Pin description 4/23 Pin Symbol 1 GND 2 SD / OD Description Ground Shut down logic input (active low) / open drain (comparator output) 3 VCC W Low voltage power supply W phase 4 HIN W High side logic input for W phase 5 LIN W Low side logic input for W phase 6 OP+ Op amp non inverting input 7 OPOUT 8 OP- 9 VCC V Low voltage power supply V phase 10 HIN V High side logic input for V phase 11 LIN V Low side logic input for V phase 12 CIN Comparator input 13 VCC U Low voltage power supply for U phase 14 HIN U High side logic input for U phase 15 SD / OD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Op amp output Op amp inverting input Shut down logic input (active low) / open drain (comparator output) Low side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output Negative DC input for W phase DocID024132 Rev 4 STGIPN3H60-H Internal schematic diagram and pin configuration Figure 2: Pin layout (top view) PIN26 (*) (*) PIN17 PIN #1 ID PIN16 PIN1 (*) Dummy pin internally connected to P (positive DC input). DocID024132 Rev 4 AM09368V1 5/23 Electrical ratings STGIPN3H60-H 2 Electrical ratings 2.1 Absolute maximum ratings Table 3: Inverter part Symbol Parameter Value Unit VCES Each IGBT collector emitter voltage (VIN(1)= 0) 600 V ± IC(2) Each IGBT continuous collector current at TC = 25°C 3 A ± ICP(3) Each IGBT pulsed collector current 18 A Each IGBT total dissipation at TC = 25°C 8 W PTOT Notes: (1)Applied between HINi, LINi and GND for i = U, V, W. (2)Calculated (3)Pulse according to the iterative formula: width limited by max junction temperature. Table 4: Control part Symbol Parameter Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied between OUTU, OUTV, OUTW GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ OPAMP non-inverting input - 0.3 VCC + 0.3 V Vop- OPAMP inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied between HIN, LIN and GND - 0.3 15 V Open drain voltage - 0.3 15 V 50 V/ns VIN VSD⁄OD ∆VOUT/dT Allowed output slew rate Table 5: Total system 6/23 Symbol Parameter Value Unit VISO Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s.) 1000 V Tj Power chips operating junction temperature range -40 to 150 °C TC Module operation case temperature range -40 to 125 °C DocID024132 Rev 4 STGIPN3H60-H 2.2 Electrical ratings Thermal data Table 6: Thermal data Symbol RthJA Parameter Thermal resistance junction-ambient DocID024132 Rev 4 Value Unit 50 °C/W 7/23 Electrical characteristics STGIPN3H60-H 3 Electrical characteristics 3.1 Inverter part TJ = 25 °C unless otherwise specified. Table 7: Static Symbol VCE(sat) Parameter Collector-emitter saturation voltage Test conditions Min. Typ. Max. VCC = Vboot = 15 V, VIN(1) = 0 to 5 V, IC = 1 A - 2.15 2.6 VCC = Vboot = 15 V, TJ = 125 °C VIN(1) = 0 to 5 V, IC = 1 A, - 1.65 Unit V ICES Collector-cut off current (VIN(1) = 0 “logic state”) VCE = 550 V, VCC = VBoot = 15 V - 250 µA VF Diode forward voltage VIN(1) = 0 “logic state”, IC = 1 A - 1.7 V Unit Notes: (1)Applied between HINi, LINi and GND for i = U, V, W. Table 8: Inductive load switching time and energy Symbol ton (1) tc(on)(1) toff(1) tc(off)(1) trr Parameter Test conditions Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching energy Eoff Turn-off switching energy VDD = 300 V, VCC = Vboot = 15 V, VIN(2) = 0 to 5 V, IC = 1 A (see Figure 4: "Switching time definition") Min. Typ. Max. - 275 - - 90 - - 890 - - 125 - - 50 - - 18 - - 13 - ns µJ Notes: (1)t ON and tOFF include the propagation delay time of the internal drive. t C(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. (2)Applied 8/23 between HINi, LINi and GND for i = U, V, W. DocID024132 Rev 4 STGIPN3H60-H Electrical characteristics Figure 3: Switching time test circuit INPUT BOOT Lin BUS VBOOT>VCC +5V /SD HVG RSD Hin L OUT VCC Vcc IC DT LVG GND CP+ VCE 0 1 AM06019v3 Figure 4: Switching time definition(1) Notes: (1)Figure 4: "Switching time definition" refers to HIN, LIN inputs (active high). DocID024132 Rev 4 9/23 Electrical characteristics 3.2 STGIPN3H60-H Control part Table 9: Low voltage power supply (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VCC_hys VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn OFF threshold 10 10.5 11 V 150 µA 1 mA 0.58 V Iqccu Iqcc Undervoltage quiescent supply current Quiescent current VCC = 10 V, SD /OD = 5 V, LIN = 0, HIN = 0, CIN = 0 Vcc = 15 V, SD /OD = 5 V, LIN = 0, HIN = 0, CIN = 0 Vref Internal comparator (CIN) reference voltage 0.5 0.54 Table 10: Bootstrapped voltage (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VBS_hys VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current 70 110 µA 150 210 µA IQBS VBS quiescent current VBS < 9 V, SD /OD = 5 V, LIN = 0, HIN=5 V, CIN = 0 VBS =15 V, SD /OD = 5 V, LIN = 0, HIN=5 V, CIN = 0 RDS(on) 10/23 Bootstrap driver onresistance LVG ON DocID024132 Rev 4 120 Ω STGIPN3H60-H Electrical characteristics Table 11: Logic inputs (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Vil Low logic level voltage Vih High logic level voltage IHINh HIN logic “1” input bias current HIN = 15 V IHINI HIN logic “0” input bias current HIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ILINI LIN logic “0” input bias current LIN = 0 V SD logic “0” input bias ISDh Min. Typ. Max. Unit 0.8 V 2.25 20 20 SD = 15 V SD =0V 30 V 40 40 120 100 µA 1 µA 100 µA 1 µA 300 µA 3 µA current SD logic “1” input bias ISDI current Dt see Figure 5: "Dead time and interlocking waveform definitions" Dead time 180 ns Table 12: OPAMP characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test condition Vio Input offset voltage Iio Input offset current Input bias current Iib (1) Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Vicm Input common mode voltage range VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = + 1 V; Vo = 0 V 16 30 mA Sink, Vid = -1 V; Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/µs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Io Output short-circuit current SR 0 V 75 150 mV Notes: (1)The direction of input current is out of the IC. DocID024132 Rev 4 11/23 Electrical characteristics STGIPN3H60-H Table 13: Sense comparator characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Iib Input bias current VCIN = 1 V 3 µA Vol Open drain low level output voltage Iod = 3 mA 0.5 V 130 ns td_comp SD /OD pulled to 5 V through Comparator delay 90 100 kΩ resistor SR Slew rate CL = 180 pF; Rpu = 5 kΩ tsd Shutdown to high / low side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V 50 125 200 tisd Comparator triggering to high / low side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CIN 50 200 250 60 V/µsec ns Table 14: Truth table Logic input (VI) Condition Output SD /OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X(1) X(1) L L Interlocking half-bridge tri-state H H H L L 0 “logic state” half-bridge tri-state H L L L L 1 “logic state” low side direct driving H H L H L 1 “logic state” high side direct driving H L H L H Notes: (1)X: don’t care. 12/23 DocID024132 Rev 4 STGIPN3H60-H 3.3 Electrical characteristics Waveform definitions Figure 5: Dead time and interlocking waveform definitions DocID024132 Rev 4 13/23 Smart shutdown function 4 STGIPN3H60-H Smart shutdown function The STGIPN3H60-H integrates a comparator for fault sensing purposes. The comparator has an internal voltage reference VREF connected to the inverting input, while the noninverting input, available on pin (CIN), can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the DMOS connected to the open-drain output is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (Vil). Finally, the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. 14/23 DocID024132 Rev 4 STGIPN3H60-H Smart shutdown function Figure 6: Smart shutdown timing waveforms comp Vref C P+ H IN /LIN PROTECTION H VG/LVG SD /OD open drain gate (internal) disable tim e Fast shut down : the driver outputs are set in SD state im m ediately after the com parator triggering even if the SD signal has not yet reach the low er input threshold An approximation of the disable time is given by: SHUT DOW N CIRCUIT V BIAS where: R SD SD/OD FROM /TO CONTROLLER C SD RON_OD SM ART SD LOGIC RPD_SD AM12947v1 Please refer to Table 13: "Sense comparator characteristics (VCC = 15 V unless otherwise specified)" for internal propagation delay time details. DocID024132 Rev 4 15/23 Application circuit example 5 STGIPN3H60-H Application circuit example Figure 7: Application circuit example AM09367v1 Application designers are free to use a different scheme according with the specifications of the device. 16/23 DocID024132 Rev 4 STGIPN3H60-H 5.1 Application circuit example Guidelines  Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull down resistor is builtin for each input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. To prevent input signal oscillation, the wiring of each input should be as short as possible. By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-coupler is possible. Each capacitor should be located as close as possible to the pins of the IPM. Low inductance shunt resistors should be used for phase leg current sensing. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitors mounted close to the module pins will further improve performance.       The SD /OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: "Smart shutdown function" for detailed info). These guidelines are useful for application design to ensure the specifications of the device. For further details, please refer to the relevant application note AN4043. Table 15: Recommended operating conditions Symbol Parameter Test conditions Min. VPN Supply voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent Arm-short For each input signal 1.5 fPWM PWM input signal -40°C < Tc < 100 °C -40°C < Tj < 125 °C TC Case operation temperature DocID024132 Rev 4 13.5 Typ. Max. Unit 300 500 V 15 18 V 18 V µs 25 kHz 100 °C 17/23 Package information 6 STGIPN3H60-H Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 18/23 DocID024132 Rev 4 STGIPN3H60-H 6.1 Package information NDIP-26L type C package information Figure 8: NDIP-26L type C package outline 8278949_7 DocID024132 Rev 4 19/23 Package information STGIPN3H60-H Table 16: NDIP-26L type C mechanical data mm Dim. Min. Typ. A 4.40 A1 0.80 1.00 1.20 A2 3.00 3.10 3.20 A3 1.70 1.80 1.90 A4 5.70 5.90 6.10 b 0.53 b1 0.52 0.72 b2 0.83 b3 0.82 c 0.46 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.50 0.77 1.00 D2 0.35 0.53 0.60 0.68 1.02 0.90 0.98 0.59 D3 20/23 Max. 0.70 29.55 E 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eB1 16.10 16.40 16.70 eB2 21.18 21.48 21.78 L 1.24 1.39 1.54 DocID024132 Rev 4 STGIPN3H60-H 6.2 Package information NDIP-26L packing information Figure 9: NDIP-26L tube dimensions (dimensions are in mm) Notes: 8313150_3 Table 17: Shipping details Parameter Value Base quantity 17 pcs Bulk quantity 476 pcs DocID024132 Rev 4 21/23 Revision history 7 STGIPN3H60-H Revision history Table 18: Document revision history 22/23 Date Revision Changes 15-Jan-2013 1 Initial release. 02-May-2013 2 Modified: Figure 3 on page 8, Section 4 on page 14 and Figure 6 on page 15. 14-Mar-2014 3 Updated Figure 3: Switching time test circuit, Table 9: Bootstrapped voltage (VCC = 15 V unless otherwise specified) and Table 10: Logic inputs (VCC = 15 V unless otherwise specified). Updated Section 6: Package mechanical data. 08-Sep-2016 4 Updated Section 6.1: "NDIP-26L type C package information" and Section 6.2: "NDIP-26L packing information" Minor text changes DocID024132 Rev 4 STGIPN3H60-H IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID024132 Rev 4 23/23