STGIPN3H60

STGIPN3H60 Datasheet SLLIMM-nano IPM, 3 A, 600 V, 3-phase inverter bridge IGBT Features • • • • • • • • • • • IPM 3 A, 600 V, 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes Optimized for low electromagnetic interferences VCE(sat) negative temperature coefficient 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors Undervoltage lockout Internal bootstrap diode Interlocking function Shutdown function Comparator for fault protection against overtemperature and overcurrent Op-amp for advanced current sensing Optimized pinout for easy board layout NDIP-26L Applications • • • • • 3-phase inverters for motor drives Dish washers Refrigerator compressors Air-conditioning fans Draining and recirculation pumps Description Product status STGIPN3H60 Device summary Order code STGIPN3H60 Marking GIPN3H60 Package NDIP-26L Packing Tube This intelligent power module implements a compact, high performance AC motor drive in a simple, rugged design. It is composed of six IGBTs with freewheeling diodes and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM™ is a trademark of STMicroelectronics. DS7272 - Rev 8 - March 2020 For further information contact your local STMicroelectronics sales office. www.st.com STGIPN3H60 Internal schematic diagram and pin configuration 1 Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram PIN 1 PIN 26 GND NW GND SD-OD HVG Vcc W VCC OUT W, OUT W LVG HIN W HIN SD-OD LIN W VBOOT LIN Vboot W OP+ GND OPOUT OP+ OPOUT NV OPVcc V OP- HVG VCC OUT V, OUT V LVG HIN V HIN SD-OD LIN V VBOOT LIN Vboot V CIN GND CIN NU HVG Vcc U VCC OUT U,OUT U LVG HIN U SD-OD LIN U PIN 16 P HIN SD-OD LIN VBOOT Vboot U PIN 17 AM09916v1 DS7272 - Rev 8 page 2/20 STGIPN3H60 Internal schematic diagram and pin configuration Table 1. Pin description DS7272 - Rev 8 Pin Symbol Description 1 GND 2 SD / OD 3 VCC W 4 HIN W High-side logic input for W phase 5 LIN W Low-side logic input for W phase 6 OP+ 7 OPOUT 8 OP- 9 VCC V Low voltage power supply V phase 10 HIN V High-side logic input for V phase 11 LIN V Low-side logic input for V phase 12 CIN 13 VCC U Low voltage power supply for U phase 14 HIN U High-side logic input for U phase 15 SD / OD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Ground Shutdown logic input (active low) / open-drain (comparator output) Low voltage power supply W phase Op-amp non inverting input Op-amp output Op-amp inverting input Comparator input Shutdown logic input (active low) / open-drain (comparator output) Low-side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output Negative DC input for W phase page 3/20 STGIPN3H60 Internal schematic diagram and pin configuration Figure 2. Pin layout (top view) PIN26 (*) (*) PIN17 PIN #1 ID PIN1 (*) Dummy pin internally connected to P (positive DC input). DS7272 - Rev 8 PIN16 AM09368V1 page 4/20 STGIPN3H60 Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 2. Inverter part Symbol VCES Parameter (1)= Each IGBT collector emitter voltage (VIN 0) Value Unit 600 V ± IC Continuous collector current each IGBT(TC = 25 °C) 3 A ± ICP (2) Pulsed collector current each IGBT (less than 1 ms) 18 A Total power dissipation each IGBT(TC = 25 °C) 9.7 W PTOT 1. Applied between HINi, LIN i and GND for i = U, V, W. 2. Pulse width limited by max. junction temperature. Table 3. Control part Symbol VOUT Parameter Output voltage applied between OUTU, OUTV, OUTW - GND Min. Max. Unit Vboot - 21 Vboot + 0.3 V VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ Op-amp non-inverting input - 0.3 VCC + 0.3 V Vop- Op-amp inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied among HIN, LIN and GND - 0.3 15 V VSD/OD Open-drain voltage - 0.3 15 V dVout/dt Allowed output slew rate 50 V/ns VIN Table 4. Total system Symbol VISO DS7272 - Rev 8 Parameter Isolation withstand voltage applied between each pin and heat sink plate (AC voltage, t = 60 s) Value Unit 1000 Vrms TJ Power chip operating junction temperature range -40 to 150 °C TC Module operation case temperature range -40 to 125 °C page 5/20 STGIPN3H60 Thermal data 2.2 Thermal data Table 5. Thermal data Symbol Rth(j-c) Rth(j-a) DS7272 - Rev 8 Parameter Value Thermal resistance junction-case single IGBT 12.8 Thermal resistance junction-case single diode 15.5 Thermal resistance junction-ambient (per module) Unit °C/W 22 page 6/20 STGIPN3H60 Electrical characteristics 3 Electrical characteristics 3.1 Inverter part TJ = 25 °C unless otherwise specified. Table 6. Static Symbol Parameter Test conditions Min. Typ. Max. - 2.15 2.6 VCC = Vboot = 15 V, VIN (1)= 0 to 5 V, IC = 1 A VCE(sat) Collector-emitter saturation voltage V VCC = Vboot = 15 V, VIN (1)= Unit 0 to 5 V, IC = 1 A, - 1.65 TJ = 125 °C ICES VF Collector cut-off current (VIN (1)= 0 “logic state”) Diode forward voltage VCE = 550 V, VCC = 15 V , VBS = 15 V VIN (1)= 0 “logic state”, IC = 1 A - 250 µA - 1.7 V Unit 1. Applied between HINi, LIN i and GND for i = U, V, W (LIN inputs are active low). Table 7. Inductive load switching time and energy Symbol ton (1) tc(on) (1) toff (1) tc(off) (1) trr Parameter Test conditions Turn-on time Min. Typ. Max. - 275 - Crossover time (on) VDD = 300 V, - 90 - Turn-off time VCC = Vboot = 15 V, - 890 - - 125 - - 50 - - 18 - - 13 - Crossover time (off) Reverse recovery time Eon Turn-on switching energy Eoff Turn-off switching energy VIN (2)= 0 to 5 V, IC = 1 A (see Figure 4. Switching time definition) ns µJ 1. tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving conditions. 2. Applied between HINi, LIN i and GND for i = U, V, W ( LIN inputs are active low). DS7272 - Rev 8 page 7/20 STGIPN3H60 Inverter part Figure 3. Switching time test circuit INPUT BOOT /Lin BUS VBOOT>VCC +5V HVG /SD RSD Hin L OUT VCC Vcc IC DT LVG GND CP+ VCE 0 1 AM09366v1 Figure 4. Switching time definition 100% IC 100% IC t rr IC VCE VIN VIN t ON VIN(ON) VCE IC t C(ON) 10% IC 90% IC 10% VCE (a) turn-on t OFF VIN(OFF) t C(OFF) 10% VCE 10% IC (b) turn-off AM09223V1 Figure 4. Switching time definition refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. DS7272 - Rev 8 page 8/20 STGIPN3H60 Control part 3.2 Control part (VCC = 15 V unless otherwise specified). Table 8. Low voltage power supply Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn-ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn-OFF threshold 10 10.5 11 V 150 µA 1 mA VCC_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current Iqcc Quiescent current Vref Internal comparator (CIN) reference voltage VCC = 15 V, SD /OD = 5 V, LIN = 5 V, HIN = 0 V, CIN = 0 V Vcc = 15 V, SD /OD = 5 V, LIN = 5 V, HIN = 0 V, CIN = 0 V 0.5 0.54 0.58 V Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn-ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn-OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current 70 110 µA IQBS VBS quiescent current 200 300 µA Table 9. Bootstrapped voltage Symbol VBS_hys RDS(on) Parameter Bootstrap driver on-resistance Test conditions VBS < 9 V SD /OD = 5 V, LIN and HIN = 5 V, CIN = 0 V VBS = 15 V SD /OD = 5 V, LIN and HIN = 5 V, CIN = 0 V LVG ON 120 Ω Table 10. Logic inputs Symbol Test conditions Min. Typ. Max. Unit Vil Low logic level voltage 0.8 1.1 V Vih High logic level voltage 1.9 2.25 V 260 µA 1 µA 20 µA 1 µA 300 µA 3 µA IHINh HIN logic “1” input bias current HIN = 15 V IHINI HIN logic “0” input bias current HIN = 0 V ILINI LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V ISDI SD logic “1” input bias current SD = 0 V Dead time see Figure 5. Dead time and interlocking waveform definitions Dt DS7272 - Rev 8 Parameter 110 3 30 175 6 120 180 ns page 9/20 STGIPN3H60 Control part Table 11. Op-amp characteristics Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Input bias current (1) Test conditions Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Vicm Input common mode voltage range VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = + 1 V; Vo = 0 V 16 30 mA Sink, Vid = -1 V; Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/µs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Min. Typ. Io SR Output short-circuit current 0 V 75 150 mV 1. The direction of the input current is out of the IC. Table 12. Sense comparator characteristics Symbol Test conditions Max. Unit Iib Input bias current VCIN = 1 V 1 µA Vol Open-drain low level output voltage Iod = 3 mA 0.5 V 130 ns td_comp DS7272 - Rev 8 Parameter Comparator delay SD /OD pulled to 5 V 90 through 100 kΩ resistor SR Slew rate CL = 180 pF; Rpu = 5 kΩ tsd Shutdown to high / low-side driver propagation delay VOUT = 0, Vboot = VCC, tisd Comparator triggering to high / low-side driver turn-off propagation delay VIN = 0 to 3.3 V 60 50 125 V/µs 200 ns Measured applying a voltage step from 0 V to 3.3 V to pin CIN 50 200 250 page 10/20 STGIPN3H60 Waveform definitions Table 13. Truth table Logic input (VI) Condition SD /OD Output LIN HIN LVG HVG (1) X(1) L L Shutdown enable half-bridge tri-state L Interlocking half-bridge tri-state H L H L L 0 “logic state” half-bridge tri-state H H L L L 1 “logic state” low-side direct driving H L L H L 1 “logic state” high-side direct driving H H H L H X 1. X: don’t care. 3.3 Waveform definitions Figure 5. Dead time and interlocking waveform definitions INTE RLO CKIN G INTE RLO CKIN G LIN HIN CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME LVG DT HL DT LH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DT LH DT HL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDETHE DEADTIME: DEAD TIME HIN LVG DT HL DT LH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDETHE DEADTIME: DIRECT DRIVING HIN LVG DT LH DT HL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be conn ected together and driven by just one control signal DS7272 - Rev 8 page 11/20 STGIPN3H60 Shutdown function 4 Shutdown function The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring. Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time. For an effective design of the shutdown circuit, please refer to Application note AN4966. Figure 6. Shutdown timing waveforms GADG250120171515FSR V REF CI N H IN or LIN U V, W H VG or LVG PROTECT ION SD /OD or T/SD/OD A B open -drain ga te (interna l) A B ∗ ∗ ∗ ∗ ≅ ∗ _ ∗ RSD and CSD external circuitry must be designed to ensure Please refer to AN4966 for further details. * RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin. DS7272 - Rev 8 page 12/20 STGIPN3H60 Application circuit example 5 Application circuit example Figure 7. Application circuit example AM09367v1 Application designers are free to use a different scheme according to the specifications of the device. DS7272 - Rev 8 page 13/20 STGIPN3H60 Guidelines 5.1 Guidelines • • • • • • • • Input signal HIN is active high logic. A pull-down resistor of 85 kΩ (typ.) is built-in for each high-side input. If an external RC filter is used for noise immunity, attention should be given to the variation of the input signal level. Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low-side input. To avoid input signal oscillation, the wiring of each input should be as short as possible. By integrating an application specific type HVIC inside the module, direct coupling to the MCU terminals without an optocoupler is possible. Each capacitor should be located as close as possible to pins of IPM. Low inductance shunt resistors should be used for phase leg current sensing. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitors mounted close to the module pins improve the performance. The SD /OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Smart shutdown function for detailed info). These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note AN4043. Table 14. Recommended operating conditions Symbol Test conditions Min. VPN Supply voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCC-GND VBS High-side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to avoid arm-short For each input signal 1.5 fPWM PWM input signal TC DS7272 - Rev 8 Parameter Case operation temperature -40 °C < TC < 100 °C -40 °C < TJ < 125 °C 13.5 Typ. Max. Unit 300 500 V 15 18 V 18 V µs 25 kHz 100 °C page 14/20 STGIPN3H60 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 NDIP-26L type C package information Figure 8. NDIP-26L type C package outline 8278949_7 DS7272 - Rev 8 page 15/20 STGIPN3H60 NDIP-26L type C package information Table 15. NDIP-26L type C mechanical data Dim. mm Min. Typ. A 4.40 A1 0.80 1.00 1.20 A2 3.00 3.10 3.20 A3 1.70 1.80 1.90 A4 5.70 5.90 6.10 b 0.53 b1 0.52 b2 0.83 b3 0.82 c 0.46 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.50 0.77 1.00 D2 0.35 0.53 0.70 0.72 0.60 0.68 1.02 0.90 0.98 0.59 D3 DS7272 - Rev 8 Max. 29.55 E 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eB1 16.10 16.40 16.70 eB2 21.18 21.48 21.78 L 1.24 1.39 1.54 page 16/20 STGIPN3H60 NDIP-26L packing information 6.2 NDIP-26L packing information Figure 9. NDIP-26L tube (dimensions are in mm) Notes: ±0.1 1- Material: extrused/transparent PVC 0.80 mm thickness 10E6~10E11/SQ PVC 2- General tolerance unless otherwise specified: ±0.25 mm 8313150_3 Table 16. Shipping details DS7272 - Rev 8 Parameter Value Base quantity 17 pieces Bulk quantity 476 pieces page 17/20 STGIPN3H60 Revision history Table 17. Document revision history Date Revision Changes 23-Jun-2011 1 Initial release. 23-Dec-2011 2 Document status promoted from preliminary data to datasheet. Added Figure 9 on page 20. 03-Jul-2012 3 Modified: Min. and Max. value Table 4 on page 6. Added: Table 14 on page 17. Updated Figure 3: Switching time test circuit, Figure 6: Smart shutdown timing waveforms. 14-Mar-2014 4 28-Aug-2014 5 12-Nov-2014 6 Updated Table 9: Bootstrapped voltage (VCC = 15 V unless otherwise specified), Table 10: Logic inputs (VCC = 15 V unless otherwise specified). Updated Section 6: Package mechanical data. Updated unit in Table 9: Bootstrapped voltage (VCC = 15 V unless otherwise specified) Updated unit for Slew rate parameter in Table 11.: OPAMP characteristics (VCC = 15 V unless otherwise specified) Updated 6: Package mechanical data. 16-Mar-2017 7 Updated Section 6.1: "NDIP-26L type C package information" and Section 6.2: "NDIP-26L packing information". Minor text changes. Modified title, applications and description on cover page. 02-Mar-2020 8 Modified Table 2. Inverter part, Table 5. Thermal data, Table 6. , Table 8. Low voltage power supply, Table 12. Sense comparator characteristics, Section 4 Shutdown function. Minor text changes. DS7272 - Rev 8 page 18/20 STGIPN3H60 Contents Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5 Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.1 6 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.1 NDIP-26L type C package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 NDIP-26L packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DS7272 - Rev 8 page 19/20 STGIPN3H60 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS7272 - Rev 8 page 20/20