STGIPNS3H60T-H

STGIPNS3H60T-H Datasheet SLLIMM-nano IPM, 3 A, 600 V, 3-phase inverter IGBT Features 16 • 17 1 • • • 26 NSDIP-26L • • • • • • • • • IPM 3 A, 600 V, 3-phase inverter IGBT including control ICs for gate driving and freewheeling diodes Optimized for low electromagnetic interference VCE(sat) negative temperature coefficient 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down/ pull-up resistors Undervoltage lockout Internal bootstrap diode Interlocking function Shutdown function Comparator for fault protection against overcurrent Op-amp for advanced current sensing Optimized pinout for easy board layout NTC for temperature control (UL 1434 CA 2 and 4) Moisture sensitivity level (MSL) 3 for SMD package Applications • • 3-phase inverters for motor drives Roller shutters, dish washers, refrigerator compressors, airconditioning fans, draining and recirculation pumps Description Product status STGIPNS3H60T-H Device summary Order code STGIPNS3H60T-H Marking GIPNS3H60T-H Package NSDIP-26L Packing Tape and reel This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six IGBTs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics. DS12011 - Rev 4 - October 2019 For further information contact your local STMicroelectronics sales office. www.st.com STGIPNS3H60T-H Internal schematic diagram and pin configuration 1 Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram N W (26) GND (1) T / SD / OD (2) NTC Vcc W (3) HIN W (4) W, OUT W (25) GND HVG VCC HIN OUT Vboot W (24) LVG SD/OD LINW (5) LIN Vboot OP+ (6) N V (23) OPOUT (7) GND OP+ OPOUT OP- (8) OP- VCC Vcc V (9) HIN HVG V, OUT V (22) OUT LVG SD/OD HIN V (10) LIN Vboot Vboot V (21) LIN V (11) CIN (12) GND N U (20) CIN HVG Vcc U (13) VCC HIN U (14) HIN OUT U, OUT U (19) LVG SD/OD LIN Vboot P (18) T / SD / OD (15) LIN U (16) Vboot U (17) GADG250120171448FSR DS12011 - Rev 4 page 2/23 STGIPNS3H60T-H Internal schematic diagram and pin configuration Table 1. Pin description DS12011 - Rev 4 Pin Symbol Description 1 GND 2 T/SD/ OD 3 VCC W Low voltage power supply W phase 4 HIN W High-side logic input for W phase 5 LIN W Low-side logic input for W phase 6 OP+ 7 OPOUT 8 OP- 9 VCC V Low voltage power supply V phase 10 HIN V High-side logic input for V phase 11 LIN V Low-side logic input for V phase 12 CIN 13 VCC U Low voltage power supply for U phase 14 HIN U High-side logic input for U phase 15 T/SD/OD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Ground NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) Op-amp non inverting input Op-amp output Op-amp inverting input Comparator input NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) Low-side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output Negative DC input for W phase page 3/23 STGIPNS3H60T-H Internal schematic diagram and pin configuration Figure 2. Pin layout (top view) (*) (*) PIN #1 ID (*) Dummy pin internally connected to P (positive DC input). DS12011 - Rev 4 page 4/23 STGIPNS3H60T-H Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 2. Inverter part Symbol VCES Parameter (1)= Collector-emitter voltage for each IGBT (VIN 0 V) Value Unit 600 V ±IC Continuous collector current each IGBT (TC = 25 °C) 3 A ±ICP (2) Pulsed collector current each IGBT (less than 1 ms) 6 A Total power dissipation each IGBT (TC = 25 °C) 9 W PTOT 1. Applied among HINi, LINi and GND for i = U, V, W 2. Pulse width limited by maximum junction temperature. Table 3. Control part Symbol Parameter Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied among OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ Op-amp non-inverting input - 0.3 VCC + 0.3 V Vop- Op-amp inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied among HIN, LIN and GND - 0.3 15 V Open-drain voltage - 0.3 15 V 50 V/ns VIN VT/SD/OD dvout/dt Allowed output slew rate Table 4. Total system Symbol VISO DS12011 - Rev 4 Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 s) Value Unit 1000 Vrms TJ Power chips operating junction temperature -40 to 150 °C TC Module case operation temperature -40 to 125 °C page 5/23 STGIPNS3H60T-H Thermal data 2.2 Thermal data Table 5. Thermal data Symbol Rth(j-c) Rth(j-a) DS12011 - Rev 4 Parameter Value Unit Thermal resistance junction-case single IGBT 13.8 °C/W Thermal resistance junction-case single diode 17.4 °C/W 24 °C/W Thermal resistance junction-ambient (per module) page 6/23 STGIPNS3H60T-H Electrical characteristics 3 Electrical characteristics 3.1 Inverter part TJ = 25 °C unless otherwise specified Table 6. Static Symbol Parameter Test conditions VCC = Vboot = 15 V, VIN(1) = 0 to 5 V, IC = 1 A VCE(sat) Collector-emitter saturation voltage Min. Typ. Max. - 2.15 2.6 V VCC = Vboot = 15 V, (1) VIN = 0 to 5 V, IC = 1 A, Unit - 1.65 TJ = 125 °C ICES VF Collector-cut off current (VIN(1) = 0 “logic state”) Diode forward voltage VCE = 550 V, VCC = 15 V, VBS=15 V VIN(1) = 0 “logic state”, IC = 1 A - 250 µA - 1.7 V Unit 1. Applied among HINi, LINi and GND for i = U,V,W. Table 7. Inductive load switching time and energy Symbol (1) ton tc(on)(1) (1) toff tc(off)(1) trr Parameter Test conditions Turn-on time Min. Typ. Max. - 275 - Crossover time (on) VDD = 300 V, - 90 - Turn-off time VCC = Vboot = 15 V, - 890 - - 125 - - 50 - - 18 - - 13 - Crossover time (off) Reverse recovery time Eon Turn-on switching energy Eoff Turn-off switching energy VIN(2) = 0 to 5 V, IC = 1 A (see Figure 4. Switching time definition) ns µJ 1. ton and toff include the propagation delay time of the internal drive. tc(on) and tc(off) are the switching times of IGBT itself under the internally given gate driving condition. 2. Applied among HINi, LINi and GND for i = U,V,W. DS12011 - Rev 4 page 7/23 STGIPNS3H60T-H Inverter part Figure 3. Switching time test circuit AM06019v2 Figure 4. Switching time definition 100% IC 100% IC t rr IC VCE VIN VIN t ON VIN(ON) VCE IC t C(ON) 10% IC 90% IC 10% VCE t OFF VIN(OFF) (a) turn-on t C(OFF) 10% VCE 10% IC (b) turn-off ADG090820161404MT Figure 4. Switching time definition refers to HIN, LIN inputs (active high). DS12011 - Rev 4 page 8/23 STGIPNS3H60T-H Control part 3.2 Control part VCC = 15 V unless otherwise specified Table 8. Low voltage power supply Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn-ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn-OFF threshold 10 10.5 11 V 150 µA 1 mA VCC_hys Iqccu Iqcc Parameter Test conditions VCC = 15 V, T/SD/OD = 5 V, LIN = 0 V, HIN = 0 V, Undervoltage quiescent supply current CIN = 0 V VCC = 15 V, T/SD/OD = 5 V, LIN = 0 V, HIN = 0 V, Quiescent current CIN = 0 V Vref Internal comparator (CIN) reference voltage 0.5 0.54 0.58 V Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn-ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn-OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current 70 110 µA 200 300 µA Table 9. Bootstrapped voltage Symbol VBS_hys IQBS Parameter VBS quiescent current Test conditions VBS < 9 V, T/SD/OD = 5 V, LIN = 0 V and HIN = 5 V, CIN = 0 V VBS = 15 V, T/SD/OD = 5 V, LIN = 0 V and HIN = 5 V, CIN = 0 V RDS(on) DS12011 - Rev 4 Bootstrap driver on-resistance LVG ON 120 Ω page 9/23 STGIPNS3H60T-H Control part Table 10. Logic inputs Symbol Parameter Test conditions Vil Low logic level voltage Vih High logic level voltage IHINh HIN logic “1” input bias current HIN = 15 V IHINI HIN logic “0” input bias current Min. Typ. Max. Unit 0.8 V 2.25 100 µA HIN = 0 V 1 µA ILINI LIN logic “0” input bias current LIN = 0 V 1 µA ILINh LIN logic “1” input bias current LIN = 15 V 20 40 100 µA ISDh SD logic “0” input bias current SD = 15 V 200 350 500 µA ISDI SD logic “1” input bias current SD = 0 V 3 µA Dead time (see Figure 9. Dead time and interlocking waveform definitions) Dt 20 V 40 180 ns Table 11. Op-amp characteristics Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Input bias current (1) Test condition Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA 75 150 mV Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = + 1 V, Vo = 0 V 16 30 mA Sink, Vid = -1 V, Vo = VCC 50 80 mA 2.5 3.8 V/µs Io SR Output short-circuit current Slew rate Vi = 1 - 4 V, CL = 100 pF, unity gain GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB 1. The direction of input current is out of the IC. DS12011 - Rev 4 page 10/23 STGIPNS3H60T-H Control part Table 12. Sense comparator characteristics Symbol Iib Parameter Test conditions Min. Typ. Max. Unit Input bias current VCIN = 1 V 1 µA Vod Open-drain low level output voltage Iod = 3 mA 0.5 V RON_OD Open-drain low level output Iod = 3 mA RPD_SD SD pull-down resistor (1) td_comp Comparator delay T/SD/OD pulled to 5 V through 100 kΩ resistor 90 SR Slew rate CL = 180 pF; Rpu = 5 kΩ 60 tsd Shutdown to high- / low-side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V tisd Comparator triggering to high- / low-side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CIN 50 166 Ω 125 kΩ 130 ns V/µs 125 200 ns 50 200 250 1. Equivalent value derived from the resistances of three drivers in parallel. Table 13. Truth table Condition Logic input (VI) Output T/SD/OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X(1) X(1) L L Interlocking half-bridge tri-state H H H L L 0 “logic state” half-bridge tri-state H L L L L 1 “logic state” low- side direct driving H H L H L 1 “logic state” high- side direct driving H L H L H 1. X: don’t care. DS12011 - Rev 4 page 11/23 STGIPNS3H60T-H Control part 3.2.1 NTC thermistor Figure 5. Internal structure of SD and NTC GADG020120181050SA RPD_SD: equivalent value as result of resistances of three drivers in parallel. Figure 6. Equivalent resistance (NTC//RPD_SD) 140 Equivalent Resistance (kΩ) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS12011 - Rev 4 page 12/23 STGIPNS3H60T-H Control part Figure 7. Equivalent resistance (NTC//RPD_SD) zoom 14 12 Equivalent Resistance (kΩ) 10 8 6 4 2 0 70 80 90 100 110 120 Temperature (°C) Figure 8. Voltage of T/SD/OD pin according to NTC temperature 5.0 SD/OD: high 4.5 VBias = 5 V R SD = 2.2 kΩ VSD(V) 4.0 3.5 VBias = 3.3 V RSD = 1.0 kΩ 3.0 2.5 2.0 25 50 75 100 125 Temperature (°C) DS12011 - Rev 4 page 13/23 STGIPNS3H60T-H Waveform definitions 3.3 Waveform definitions CKIN GG ERO L INT INT ERO L CKIN G Figure 9. Dead time and interlocking waveform definitions GADG080120181131SA DS12011 - Rev 4 page 14/23 STGIPNS3H60T-H Shutdown function 4 Shutdown function The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring. Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time. For an effective design of the shutdown circuit, please refer to Application note AN4966. Figure 10. Shutdown timing waveforms GADG250120171515FSR V REF CI N H IN or LIN U V, W H VG or LVG PROTECT ION SD /OD or T/SD/OD A B open -drain ga te (interna l) A B ∗ ∗ ∗ ∗ ≅ ∗ _ ∗ RSD and CSD external circuitry must be designed to ensure Please refer to AN4966 for further details. * RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin. DS12011 - Rev 4 page 15/23 DS12011 - Rev 4 RS + R1 5V / 3.3V - VC C C vc c C SD R SD 5V / 3.3V ADC C2 R1 HIN W R3 R2 R4 R1 R1 R1 SD Temp. Monitoring MICROCONTROLLER LIN W ADC HIN V LIN V R1 HIN U RS R1 R5 C1 C1 C1 C1 DZ1 LIN U (16) Vcc W (3) HIN W (4) LINW (5) OP+ (6) OPOUT (7) OP- (8) Vcc V (9) HIN V (10) LIN V (11) GND (1) T / SD / OD (2) C OP C SF CIN (12) Vcc U (13) HIN U (14) T / SD / OD (15) SGN_GN D R SF C1 C1 NTC LIN GND VCC HIN SD/OD LIN GND OPOUT OP- VCC HIN SD/OD LIN GND VCC HIN SD/OD LVG OUT HVG Vboot OP+ LVG OUT HVG Vboot CIN LVG OUT HVG Vboot RS N W (26) W, OUT W (25) Vboot W (24) N V (23) V, OUT V (22) Vboot V (21) N U (20) U, OUT U (19) P (18) Vboot U (17) Cboot W Cboot V Cboot U C3 C3 C3 DZ2 DZ2 DZ2 PWR_GN D Rshunt M C4 Cvdc - + VDC 5 LIN U Application circuit example STGIPNS3H60T-H Application circuit example Figure 11. Application circuit example GAD250720161156FSR Application designers are free to use a different scheme according to the device specifications. page 16/23 STGIPNS3H60T-H Guidelines 5.1 Guidelines • • Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor. • The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin. • The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin. • The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. • • The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). • By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible. Low-inductance shunt resistors have to be used for phase leg current sensing. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. • • • These guidelines ensure the device specifications for application designs. For further details, please refer to the relevant application note. Table 14. Recommended operating conditions Symbol Test conditions VPN Supply voltage Applied among P-Nu, Nv, Nw VCC Control supply voltage Applied to VCC-GND VBS High-side bias voltage tdead fPWM TC DS12011 - Rev 4 Parameter Blanking time to prevent arm-short PWM input signal Case operation temperature Applied to VBOOTx-OUT for x = U, V, W For each input signal -40 °C < TC < 100 °C -40 °C < TJ < 125 °C Min. 13.5 13 Typ. Max. Unit 300 500 V 15 18 V 18 V 1.5 μs 25 kHz 100 °C page 17/23 STGIPNS3H60T-H Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 NSDIP-26L package information Figure 12. NSDIP-26L package outline 8374968_4 DS12011 - Rev 4 page 18/23 STGIPNS3H60T-H NSDIP-26L package information Table 15. NSDIP-26L package mechanical data Dim. mm Min. Typ. A 3.45 A1 0.10 0.25 A2 3.00 3.10 3.20 A3 1.10 1.30 1.50 b 0.47 b1 0.45 b2 0.63 0.67 c 0.47 0.57 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.70 D2 0.45 D3 0.90 0.57 0.50 D4 0.55 29.65 E 12.35 12.45 12.55 E1 16.70 17.00 17.30 E2 0.35 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 L 1.24 1.39 1.54 L1 1.00 1.15 1.30 L2 0.25 BSC L3 2.275 REF R1 0.25 0.40 0.55 R2 0.25 0.40 0.55 0.39 0.55 S ϴ 0° ϴ1 ϴ2 DS12011 - Rev 4 Max. 8° 3° BSC 10° 12° 14° page 19/23 STGIPNS3H60T-H NSDIP-26L package information Figure 13. NSDIP-26L recommended footprint (dimensions are in mm) 8374968_4_fp DS12011 - Rev 4 page 20/23 STGIPNS3H60T-H Revision history Table 16. Document revision history Date Revision 19-Apr-2017 1 Changes Initial release Datasheet promoted from preliminary data to production data. Modified features on cover page. Modified Figure 2: "Pin layout (top view)", Table 3: "Inverter part", 09-Jan-2018 2 Table 5: "Total system", Table 6: "Thermal data", Table 9: "Low voltage power supply", Table 10: "Bootstrapped voltage", Table 13: "Sense comparator characteristics". Updated Section 6.1: "NSDIP-26L package information". Minor text changes. Removed maturity status indication from cover page. Modified Table 2. Inverter part, Table 3. Control part. 03-Apr-2018 3 Modified Section 4 Shutdown function. Added Table 14. Recommended operating conditions. Minor text changes. Modified features and applications on cover page. 15-Oct-2019 4 Modified Table 2. Inverter part, Table 5. Thermal data, Table 8. Low voltage power supply, Table 10. Logic inputs, Section 5.1 Guidelines. Updated Section 6.1 NSDIP-26L package information. Minor text changes. DS12011 - Rev 4 page 21/23 STGIPNS3H60T-H Contents Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 3.3 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.1 6 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.1 NSDIP-26L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DS12011 - Rev 4 page 22/23 STGIPNS3H60T-H IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12011 - Rev 4 page 23/23