STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Datasheet
SLLIMM-nano, 2nd series IPM, 3 A, 600 V, 3-phase inverter bridge IGBT
Features
•
•
•
•
•
IPM 3 A, 600 V, 3-phase IGBT inverter bridge including 3 control ICs for gate
driving and freewheeling diodes
3.3 V, 5 V, 15 V TTL/CMOS input comparators with hysteresis and pull-down/
pull-up resistors
Internal bootstrap diode
Optimized for low electromagnetic interference
Undervoltage lockout
VCE(SAT) negative temperature coefficient
•
•
•
•
•
•
•
•
Shutdown function
Interlocking function
Op-amp for advanced current sensing
Comparator for fault protection against overcurrent
NTC (UL 1434 CA 2 and 4)
Isolation ratings of 1500 Vrms/min.
Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ)
UL recognition: UL 1557, file E81734
•
N2DIP-26L type L
no stand-off
N2DIP-26L type Z
no stand-off
Applications
•
•
•
•
•
•
3-phase induction motor (ACIM)
Dishwasher
Fans
Kitchen hoods
PMSM / BLDC motor control
Refrigerators and freezers
Product status link
Description
STGIPQ3H60T-HLS
This second series of SLLIMM (small low-loss intelligent molded module) nano
provides a compact, high-performance AC motor drive in a simple, rugged design.
It is composed of six improved short-circuit rugged trench gate fieldstop IGBTs with
freewheeling diodes and three half-bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics with optimized switching speed.
The package is designed to allow a better and more easily screwed-on heat sink, and
is optimized for thermal performance and compactness in built-in motor applications
or other low power applications where assembly space is limited. This IPM includes a
completely uncommitted operational amplifier and a comparator that can be used to
design a fast and efficient protection circuit.
STGIPQ3H60T-HZS
Product summary
Order code: STGIPQ3H60T-HLS
Marking
GIPQ3H60T-HLS
Package
N2DIP-26L type L no
stand-off
Packing
Tube
Order code: STGIPQ3H60T-HZS
Marking
GIPQ3H60T-HZS
Package
N2DIP-26L type Z no
stand-off
Packing
Tube
DS11141 - Rev 5 - September 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Internal schematic diagram and pin configuration
1
Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
N W (26)
GND (1)
T/ SD / OD (2)
NTC
Vcc W (3)
HIN W (4)
W, OUT W (25)
GND
HVG
VCC
HIN
OUT
Vboot W (24)
LVG
SD/OD
LIN W (5)
LIN
Vboot
OP+ (6)
N V (23)
OPOUT (7)
GND
OP+
OPOUT
OP- (8)
OP-
VCC
Vcc V (9)
HIN
HVG
V, OUT V (22)
OUT
LVG
SD/OD
HIN V (10)
LIN
Vboot
Vboot V (21)
LIN V (11)
CIN (12)
GND
N U (20)
CIN
HVG
Vcc U (13)
VCC
HIN U (14)
HIN
OUT
U, OUT U (19)
LVG
SD/OD
LIN
Vboot
P (18)
T / SD / OD (15)
LIN U (16)
Vboot U (17)
GIPG300720141542SMD
DS11141 - Rev 5
page 2/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Internal schematic diagram and pin configuration
Table 1. Pin description
DS11141 - Rev 5
Pin
Symbol
Description
1
GND
2
T/SD/OD
3
VCC W
Low-voltage power supply W phase
4
HIN W
High-side logic input for W phase
5
LIN W
Low-side logic input for W phase
6
OP+
7
OPOUT
8
OP-
9
VCC V
Low-voltage power supply V phase
10
HIN V
High-side logic input for V phase
11
LIN V
Low-side logic input for V phase
Ground
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Op-amp non-inverting input
Op-amp output
Op-amp inverting input
12
CIN
13
VCC U
Comparator input
Low-voltage power supply for V phase
14
HIN U
High-side logic input for V phase
15
T/SD/OD
16
LIN U
17
Vboot U
18
P
19
U, OUTU
20
NU
Negative DC input for U phase
21
Vboot V
Bootstrap voltage for V phase
22
V, OUTV
23
NV
Negative DC input for V phase
24
Vboot W
Bootstrap voltage for W phase
25
W, OUTW
26
NW
NTC thermistor terminal/shutdown logic input (active low)/open-drain
(comparator output)
Low-side logic input for U phase
Bootstrap voltage for U phase
Positive DC input
U phase output
V phase output
W phase output
Negative DC input for W phase
page 3/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Internal schematic diagram and pin configuration
Figure 2. Pin layout (top view) - N2DIP-26L type L
PIN 26
*
*
PIN 17
Exposed pin
not connected
Exposed pin internally
connected to GND
isolated by
glue spot adding
PIN 16
PIN 1
* Dummy pins internally connected to P (positive DC input)
GADG181220181209IG
Figure 3. Pin layout (top view) - N2DIP-26L type Z
PIN 26
*
*
PIN 17
Exposed pin
not connected
PIN 1
* Dummy pins internally connected to P (positive DC input)
DS11141 - Rev 5
Exposed pin internally
connected to GND
isolated by
glue spot adding
PIN 16
GADG181220181216IG
page 4/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Electrical ratings
2
Electrical ratings
TJ = 25 °C unless otherwise specified
2.1
Absolute maximum ratings
Table 2. Inverter part
Symbol
Value
Unit
600
V
Continuous collector current for each IGBT (TC = 25 °C)
3
A
ICP(2)
Peak collector current for each IGBT (less than 1 ms)
6
A
PTOT
Total power dissipation for each IGBT (TC = 25 °C)
12
W
VCES
IC
Parameter
Collector-emitter voltage for each IGBT (VIN(1) = 0)
1. Applied among HINx, LINx and GND for x = U, V, W
2. Pulse width limited by maximum junction temperature.
Table 3. Control part
Symbol
Parameter
Min.
Max.
Unit
VCC
Low voltage power supply
-0.3
21
V
Vboot
Bootstrap voltage
-0.3
620
V
VOUT
Output voltage applied among OUTU,
OUTV, OUTW - GND
Vboot - 21
Vboot + 0.3
V
VCIN
Comparator input voltage
-0.3
VCC + 0.3
V
Vop+
Op-amp non-inverting input
-0.3
VCC + 0.3
V
Vop-
Op-amp inverting input
-0.3
VCC + 0.3
V
VIN
Logic input voltage applied among HINx,
LINx and GND
-0.3
15
V
VT/SD/OD
Open-drain voltage
-0.3
15
V
dVout/dt
Allowed output slew rate
50
V/ns
Value
Unit
1500
Vrms
Table 4. Total system
Symbol
VISO
DS11141 - Rev 5
Parameter
Isolation withstand voltage applied to each pin and heat sink plate
(AC voltage, t = 60 s)
TJ
Power chip operating junction temperature
-40 to 150
°C
TC
Operating case temperature range
-40 to 125
°C
page 5/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Thermal data
2.2
Thermal data
Table 5. Thermal data
Symbol
RthJC
DS11141 - Rev 5
Parameter
Value
Thermal resistance, junction-to-case single IGBT
10
Thermal resistance, junction-to-case single diode
15
Unit
°C/W
page 6/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Electrical characteristics
3
Electrical characteristics
TJ = 25 °C unless otherwise specified.
3.1
Inverter part
Table 6. Static
Symbol
Parameter
ICES
Collector cut-off current (VIN(1) =
0 “logic state”)
VCE(sat)
VF
Collector-emitter saturation
voltage
Test conditions
Min.
VCE = 550 V, VCC = VBoot = 15 V
Typ.
-
VCC = Vboot = 15 V, VIN(1) = 0 to 5 V,
Max.
Unit
250
μA
-
2.15
2.6
V
-
1.35
1.8
V
Min.
Typ.
Max.
Unit
Turn-on time
-
275
-
Crossover time (on)
-
90
-
-
890
-
-
125
-
-
50
-
Diode forward voltage
IC = 1 A
VIN(1) = 0 “logic state”, IC = 1 A
1. Applied among HINx, LINx and GND for x = U, V, W.
Table 7. Inductive load switching time and energy
Symbol
ton(1)
(1)
tc(on)
toff(1)
(1)
tc(off)
trr
Parameter
Turn-off time
Crossover time (off)
Reverse recovery time
Test conditions
VDD = 300 V,VCC = Vboot = 15 V,
VIN(2) = 0 to 5 V, IC = 1 A
(see Figure 5. Switching time
definition)
Eon
Turn-on switching energy
-
18
-
Eoff
Turn-off switching energy
-
13
-
ns
µJ
1. tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching times of the IGBT
itself under the internally given gate driving conditions.
2. Applied among HINx, LINx and GND for x = U, V, W.
DS11141 - Rev 5
page 7/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Inverter part
Figure 4. Switching time test circuit
AM06019v2
Figure 5. Switching time definition
100% IC
100% IC
t rr
IC
VCE
VIN
VIN
t ON
VIN(ON)
VCE
IC
t C(ON)
10% IC
90% IC 10% VCE
t OFF
VIN(OFF)
(a) turn-on
t C(OFF)
10% VCE
10% IC
(b) turn-off
AM09223V1
Figure 5. Switching time definition refers to HIN, LIN inputs (active high).
DS11141 - Rev 5
page 8/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Control part
3.2
Control part
Table 8. Low-voltage power supply
Symbol
Min.
Typ.
Max.
Unit
VCC UV hysteresis
1.2
1.5
1.8
V
VCC_thON
VCC UV turn-ON threshold
11.5
12
12.5
V
VCC_thOFF
VCC UV turn-OFF threshold
10
10.5
11
V
VCC_hys
Parameter
Test conditions
Iqccu
Undervoltage quiescent supply
current
VCC = 10 V, T/SD/OD = 5 V,
LIN = HIN = CIN = 0 V
150
µA
Iqcc
Quiescent current
VCC = 10 V, T/SD/OD = 5 V,
LIN = HIN = CIN = 0 V
1
mA
Vref
Internal comparator (CIN)
reference voltage
0.51
0.54
0.56
V
Min.
Typ.
Max.
Unit
VBS UV hysteresis
1.2
1.5
1.8
V
VBS_thON
VBS UV turn-ON threshold
11.1
11.5
12.1
V
VBS_thOFF
VBS UV turn-OFF threshold
9.8
10
10.6
V
IQBSU
Undervoltage VBS quiescent
current
70
110
µA
150
210
µA
Table 9. Bootstrapped voltage
Symbol
VBS_hys
Parameter
Test conditions
VBS < 9 V, T/SD/OD = 5 V,
LIN = 0 V and HIN = 5 V,
CIN = 0 V
VBS = 15 V, T/SD/OD = 5 V,
IQBS
VBS quiescent current
LIN = 0 V and HIN = 5 V,
CIN = 0
RDS(on)
Bootstrap driver on-resistance
LVG ON
120
Ω
Table 10. Logic inputs
Symbol
DS11141 - Rev 5
Parameter
Vil
Low logic level voltage
Vih
High logic level voltage
Test conditions
Min.
Typ.
Max.
Unit
0.8
V
2.25
IHINh
HIN logic “1” input bias current
HIN = 15 V
IHINl
HIN logic “0” input bias current
ILINl
20
V
40
100
µA
HIN = 0 V
1
µA
LIN logic “0” input bias current
LIN = 0 V
1
µA
ILINh
LIN logic “1” input bias current
LIN = 15 V
20
40
100
µA
ISDh
SD logic “0” input bias current
SD = 15 V
210
350
477
µA
ISDl
SD logic “1” input bias current
SD = 0 V
3
µA
Dt
Dead time
See Figure 10. Dead time and
interlocking waveform definitions
180
ns
page 9/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Control part
Table 11. Op-amp characteristics
Symbol
Parameter
Vio
Input offset voltage
Iio
Input offset current
Iib
Input bias current(1)
Test conditions
Min.
Typ.
Max.
Unit
6
mV
4
40
nA
100
200
nA
75
150
mV
Vic = 0 V, Vo = 7.5 V
Vic = 0 V, Vo = 7.5 V
VOL
Low level output voltage
RL = 10 kΩ to VCC
VOH
High level output voltage
RL= 10 kΩ to GND
14
14.7
V
Source, Vid = + 1 V; Vo = 0 V
16
30
mA
Sink, Vid = -1 V; Vo = VCC
50
80
mA
Slew rate
Vi = 1 - 4 V; CL = 100 pF; unity gain
2.5
3.8
V/µs
GBWP
Gain bandwidth product
Vo = 7.5 V
8
12
MHz
Avd
Large signal voltage gain
RL = 2 kΩ
70
85
dB
SVR
Supply voltage rejection ratio
vs VCC
60
75
dB
CMRR
Common mode rejection ratio
55
70
dB
Min.
Typ.
Io
SR
Output short-circuit current
1. The direction of input current is out of the IC.
Table 12. Sense comparator characteristics
Symbol
Iib
Parameter
Test conditions
Max.
Unit
Input bias current
VCIN = 1 V
-
1
µA
Vod
Open-drain low level output
voltage
Iod = 3 mA
-
0.5
V
RON_OD
Open-drain low level output
Iod = 3 mA
-
166
Ω
RPD_SD
SD pull-down resistor(1)
-
125
kΩ
td_comp
Comparator delay
T/SD/OD pulled to 5 V through
100 kΩ resistor
-
90
SR
Slew rate
CL = 180 pF, Rpu = 5 kΩ
-
60
tsd
Shutdown to high-/low-side driver
propagation delay
VOUT = 0, Vboot = VCC,
VIN = 0 to 3.3 V
-
125
tisd
Comparator triggering to
high-/ low-side driver turn-off
propagation delay
Measured applying a voltage step
from 0 V to 3.3 V to pin CIN
130
ns
V/µs
ns
-
200
1. Equivalent values as a result of the resistances of three drivers in parallel.
DS11141 - Rev 5
page 10/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Control part
Table 13. Truth table
Logic input (VI)
Conditions
Output
T/SD/OD
LIN
HIN
LVG
HVG
Shutdown enable half-bridge tri-state
L
X(1)
X(1)
L
L
Interlocking half-bridge tri-state
H
H
H
L
L
0 “logic state” half-bridge tri-state
H
L
L
L
L
1 “logic state” low-side direct driving
H
H
L
H
L
1 “logic state” high-side direct driving
H
L
H
L
H
1. X: don’t care.
3.2.1
NTC thermistor
Figure 6. Internal structure of SD and NTC
Vbias
R SD
LIN
VT/SD/OD
Vboot
SD/OD
C SD
HVG
HIN
NTC
VCC
OUT
RPD_SD
LVG
GND
CIN
RPD_SD: equivalent value as result of resistances of three drivers in parallel.
Figure 7. Equivalent resistance (NTC//RPD_SD)
140
Equivalent Resistance (kΩ)
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
DS11141 - Rev 5
page 11/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Control part
Figure 8. Equivalent resistance (NTC//RPD_SD) zoom
14
12
Equivalent Resistance (kΩ)
10
8
6
4
2
0
70
80
90
100
110
120
Temperature (°C)
Figure 9. Voltage of T/SD/OD pin according to NTC temperature
5.0
SD/OD: high
4.5
VBias = 5 V
R SD = 2.2 kΩ
VSD(V)
4.0
3.5
VBias = 3.3 V
RSD = 1.0 kΩ
3.0
2.5
2.0
25
50
75
100
125
Temperature (°C)
DS11141 - Rev 5
page 12/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Waveform definitions
3.3
Waveform definitions
DS11141 - Rev 5
CKIN
GG
ERO
L
INT
INT
ERO
L
CKIN
G
Figure 10. Dead time and interlocking waveform definitions
page 13/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Shutdown function
4
Shutdown function
The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.
The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting
input pin (CIN) can be connected to an external shunt resistor for current monitoring.
Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs,
whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which
fixes the disabling time.
For an effective design of the shutdown circuit, please refer to Application note AN4966.
Figure 11. Shutdown timing waveforms
GADG250120171515FSR
V REF
CI N
H IN or LIN
U
V, W
H VG or LVG
PROTECT ION
SD /OD
or
T/SD/OD
A
B
open -drain ga te
(interna l)
A
B
∗
∗
∗
∗
≅
∗
_
∗
RSD and CSD external circuitry must be designed to ensure
Please refer to AN4966 for further details.
* RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin.
DS11141 - Rev 5
page 14/26
DS11141 - Rev 5
RS
+
R1
5V / 3.3V
-
VC C
C vc c
C SD
R SD
5V / 3.3V
ADC
C2
R1
HIN W
R3
R2
R4
R1
R1
R1
SD
Temp.
Monitoring
MICROCONTROLLER
LIN W
ADC
HIN V
LIN V
R1
HIN U
RS
R1
R5
C1
C1
C1
C1
DZ1
LIN U (16)
Vcc W (3)
HIN W (4)
LINW (5)
OP+ (6)
OPOUT (7)
OP- (8)
Vcc V (9)
HIN V (10)
LIN V (11)
GND (1)
T / SD / OD (2)
C OP
C SF
CIN (12)
Vcc U (13)
HIN U (14)
T / SD / OD (15)
SGN_GN D
R SF
C1
C1
NTC
LIN
GND
VCC
HIN
SD/OD
LIN
GND
OPOUT
OP-
VCC
HIN
SD/OD
LIN
GND
VCC
HIN
SD/OD
LVG
OUT
HVG
Vboot
OP+
LVG
OUT
HVG
Vboot
CIN
LVG
OUT
HVG
Vboot
RS
N W (26)
W, OUT W (25)
Vboot W (24)
N V (23)
V, OUT V (22)
Vboot V (21)
N U (20)
U, OUT U (19)
P (18)
Vboot U (17)
Cboot W
Cboot V
Cboot U
C3
C3
C3
DZ2
DZ2
DZ2
PWR_GN D
Rshunt
M
C4
Cvdc
-
+
VDC
5
LIN U
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Application circuit example
Application circuit example
Figure 12. Application circuit example
GAD250720161156FSR
Application designers are free to use a different scheme according to the specifications of the device.
page 15/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Guidelines
5.1
Guidelines
•
•
Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To
avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC
filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns
and placed as close as possible to the IPM input pins.
The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on
the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a
decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible
to the Vcc pin and in parallel with the bypass capacitor.
•
The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time
constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.
•
The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally
connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases,
due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold,
the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The
capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation
time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.
•
The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with
each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close
as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W
terminals directly and separated from the main output wires.
To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener
diode (Dz2) can be placed in parallel with each Cboot.
•
•
The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the
electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be
placed as close as possible to the IPM (C4 has priority over Cvdc).
•
By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals
without an opto-couplers is possible.
Low-inductance shunt resistors have to be used for phase leg current sensing.
In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as
possible.
The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can
reduce the impact of power ground fluctuation.
•
•
•
These guidelines ensure the specifications of the device for application designs. For further details, please refer to
the relevant application note.
Table 14. Recommended operating conditions
Symbol
Test conditions
VPN
Supply voltage
Applied among P-Nu, Nv, Nw
VCC
Control supply voltage
Applied to VCC-GND
VBS
High-side bias voltage
Applied to VBOOTx-OUT for x = U,
V, W
tdead
Blanking time to prevent arm-short For each input signal
fPWM
PWM input signal
TC
DS11141 - Rev 5
Parameter
Operating case temperature
-40 °C < TC < 100 °C
-40 °C < TJ < 125 °C
Min.
13.5
13
Typ.
Max.
Unit
300
500
V
15
18
V
18
V
1.5
µs
25
kHz
100
°C
page 16/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Electrical characteristics (curves)
6
Electrical characteristics (curves)
Figure 13. Output characteristics
IC
(A) VCC = 15 V
GADG291020181423OCH
Figure 14. Vce(sat) vs collector current
VCE
(V) VCC = 15 V
5
3.0
4
2.5
3
2.0
2
1.5
1
1.0
0
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8
VCE (V)
Figure 15. IC vs case temperature
IC
(A)
GADG291020181425CCT
0.5
0
2.5
1.6
2.0
1.4
1.5
1.2
1.0
1.0
50
75
100
125
TC (°C)
Figure 17. Eon switching energy vs collector current
EON
GADG291020181425SNC
(mJ) V = 300 V, V = V
DD
CC
boot = 15 V
0.20
3
4
5
IC (A)
GADG291020181424DVF
TJ = 25 °C
TJ = 150 °C
0.6
0
1
2
3
4
5
IF (A)
Figure 18. Eoff switching energy vs collector current
GADG291020181426SFC
EOFF
(mJ) VDD = 300 V, VCC = Vboot = 15 V
0.15
TJ = 150 °C
0.10
TJ = 150 °C
0.10
TJ = 25 °C
0.05
DS11141 - Rev 5
2
0.20
0.15
0.00
0
1
0.8
VCC ≥ 15 V, TJ ≤ 150 °C
25
TJ = 150 °C
VF
(V) VCC = 15 V
1.8
0.0
0
TJ = 25 °C
Figure 16. Diode VF vs forward current
3.0
0.5
GADG071120181035VCEC
1
2
3
4
5
TJ = 25 °C
0.05
IC (A)
0.00
0
1
2
3
4
5
IC (A)
page 17/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Electrical characteristics (curves)
Figure 19. Thermal impedance for IGBT
K
Zthjc N2DIP-26L
10 -1
10 -2
10 -3
10 -5
DS11141 - Rev 5
10 -4
10 -3
10 -2
10 -1
10 0
tp (s)
page 18/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1
N2DIP-26L type L no stand-off package information
Figure 20. N2DIP-26L type L no stand-off package outline
8558322_3_typeL_NO_stand_off
DS11141 - Rev 5
page 19/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
N2DIP-26L type L no stand-off package information
Table 15. N2DIP-26L type L no stand-off mechanical data
Dim.
mm
Min.
Typ.
A
DS11141 - Rev 5
Max.
3.80
A1
0.45
0.75
1.05
A2
4.00
4.10
4.20
A3
1.70
1.80
1.90
A4
1.70
1.80
1.90
A5
8.10
8.40
8.70
A6
1.75
b
0.53
0.72
b2
0.83
1.02
c
0.46
0.59
D
32.05
D1
2.10
D2
1.85
D3
32.15
32.25
30.65
30.75
30.85
E
12.35
12.45
12.55
e
1.70
1.80
1.90
e1
2.40
2.50
2.60
eB1
14.25
14.55
14.85
L
0.85
1.05
1.25
Dia
3.10
3.20
3.30
page 20/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
N2DIP-26L type Z no stand-off package information
7.2
N2DIP-26L type Z no stand-off package information
Figure 21. N2DIP-26L type Z no stand-off package outline
8558322_3_typeZ_NO_stand_off
DS11141 - Rev 5
page 21/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
N2DIP-26L type Z no stand-off package information
Table 16. N2DIP-26L type Z no stand-off mechanical data
Dim.
mm
Min.
Typ.
A
DS11141 - Rev 5
Max.
3.80
A1
0.45
0.75
1.05
A2
4.00
4.10
4.20
A3
1.70
1.80
1.90
A4
1.70
1.80
1.90
A5
8.10
8.40
8.70
A6
1.75
b
0.53
0.72
b2
0.83
1.02
c
0.46
0.59
D
32.05
D1
2.10
D2
1.85
D3
32.15
32.25
30.65
30.75
30.85
E
12.35
12.45
12.55
e
1.70
1.80
1.90
e1
2.40
2.50
2.60
eB1
16.10
16.40
16.70
eB2
21.18
21.48
21.78
L
0.85
1.05
1.25
Dia
3.10
3.20
3.30
page 22/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
N2DIP-26L packing information
7.3
N2DIP-26L packing information
Figure 22. N2DIP-26L tube (dimensions are in mm)
DS11141 - Rev 5
page 23/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Revision history
Table 17. Document revision history
Date
Revision
Changes
08-Jul-2015
1
Initial release.
07-Oct-2015
2
Document status promoted from preliminary data to production data.
Modified features on cover page
24-Mar-2017
3
Modified Figure 4: "Internal structure of SD and NTC"
Minor text changes.
Updated package silhouette on cover page.
18-Dec-2018
4
Updated Section 1 Internal schematic diagram and pin configuration, Section
2.1 Absolute maximum ratings, Section 3.2 Control part, Section 4 Shutdown
function and Section 5.1 Guidelines.
Added Section 6 Electrical characteristics (curves).
Updated Section 7 Package information.
Minor text changes
Modified Applications on cover page
05-Sep-2022
5
Modified Table 5. Thermal data
Minor text changes.
DS11141 - Rev 5
page 24/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
Contents
Contents
1
Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3
2.1
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.1
3.3
NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5
Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1
Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.1
N2DIP-26L type L no stand-off package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2
N2DIP-26L type Z no stand-off package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3
N2DIP-26L packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DS11141 - Rev 5
page 25/26
STGIPQ3H60T-HLS, STGIPQ3H60T-HZS
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS11141 - Rev 5
page 26/26
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