STGIPS14K60T

STGIPS14K60T SLLIMM™ small low-loss intelligent molded module IPM, 3-phase inverter, 14 A, 600 V short-circuit rugged IGBT Datasheet - production data Applications • 3-phase inverters for motor drives • Home appliances, such as washing machines, refrigerators, air conditioners and sewing machines Description This intelligent power module provides a compact, high performance AC motor drive in a simple, rugged design. Combining ST proprietary control ICs with the most advanced short-circuitrugged IGBT system technology, this device is ideal for 3-phase inverters in applications such as home appliances and air conditioners. SLLIMM™ is a trademark of STMicroelectronics. SDIP-25L Features • IPM 14 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes • Short-circuit rugged IGBTs • VCE(sat) negative temperature coefficient • 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull-down / pull-up resistors • Undervoltage lockout • Internal bootstrap diode • Interlocking function • Shutdown function • DBC substrate leading to low thermal resistance • Isolation rating of 2500 Vrms/min • 4.7 kΩ NTC for temperature control • UL Recognized: UL1557 file E81734 Table 1. Device summary Order code Marking Package Packing STGIPS14K60T GIPS14K60T SDIP-25L Tube April 2015 This is information on a product in full production. DocID018534 Rev 5 1/19 www.st.com Contents STGIPS14K60T Contents 1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 3.2 4 6 2/19 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 5 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 SDIP-25L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DocID018534 Rev 5 STGIPS14K60T 1 Internal block diagram and pin configuration Internal block diagram and pin configuration Figure 1. Internal block diagram AM09320v2 DocID018534 Rev 5 3/19 19 Internal block diagram and pin configuration STGIPS14K60T Table 2. Pin description Pin n° Symbol Description 1 OUTU High side reference output for U phase 2 Vboot U Bootstrap voltage for U phase 3 LINU Low side logic input for U phase 4 HINU High side logic input for U phase 5 VCC Low voltage power supply 6 OUTV High side reference output for V phase 7 Vboot V Bootstrap voltage for V phase 8 GND Ground 9 LINV Low side logic input for V phase 10 HINV High side logic input for V phase 11 OUTW High side reference output for W phase 12 Vboot W Bootstrap voltage for W phase 13 LINW Low side logic input for W phase 14 HINW High side logic input for W phase 15 SD Shut down logic input (active low) 16 T1 NTC thermistor terminal 17 NW Negative DC input for W phase 18 W W phase output 19 P Positive DC input 20 NV 21 V V phase output 22 P Positive DC input 23 NU Negative DC input for U phase 24 U U phase output 25 P Positive DC input Negative DC input for V phase Figure 2. Pin layout (bottom view)                 0$5.,1*$5($  4/19     DocID018534 Rev 5     STGIPS14K60T Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol VPN Parameter Value Unit 450 V 500 V 600 V Each IGBT continuous collector current at TC = 25°C 14 A Each IGBT pulsed collector current 30 A Each IGBT total dissipation at TC = 25°C 42 W Short circuit withstand time, VCE = 0.5 V(BR)CES TJ = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0 ÷ 5 V 5 µs Supply voltage applied between P - NU, NV, NW VPN(surge) Supply voltage (surge) applied between P - NU, NV, NW VCES ± IC (2) ± ICP (3) PTOT tscw Each IGBT collector emitter voltage (VIN(1) = 0) 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: Tj ( max ) – TC IC ( T C ) = ------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 3. Pulse width limited by max junction temperature Table 4. Control part Symbol Parameter Min. Max. Unit VOUT Output voltage applied between OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V VIN Logic input voltage applied between HIN, LIN and GND - 0.3 15 V VSD SD voltage - 0.3 15 V 50 V/ns Vboot - 21 Vboot + 0.3 dVOUT/dt Allowed output slew rate V Table 5. Total system Symbol VISO Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 sec.) Value Unit 2500 V TC Module case operation temperature -40 to 125 °C TJ Power chips operating junction temperature -40 to 150 °C DocID018534 Rev 5 5/19 19 Electrical ratings 2.2 STGIPS14K60T Thermal data Table 6. Thermal data Symbol RthJC 6/19 Parameter Value Unit Thermal resistance junction-case single IGBT 3 °C/W Thermal resistance junction-case single diode 5.5 °C/W DocID018534 Rev 5 STGIPS14K60T 3 Electrical characteristics Electrical characteristics TJ = 25 °C unless otherwise specified. Table 7. Inverter part Value Symbol VCE(sat) ICES VF Parameter Test conditions Unit Min. Typ. Max. VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A - 2.1 2.5 VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 7 A, TJ = 125 °C - Collector-cut off current (VIN(1)= 0 “logic state”) VCE = 550 V, VCC = VBoot = 15 V - 150 µA Diode forward voltage VIN(1) = 0 “logic state”, IC = 7 A - 2.1 V Collector-emitter saturation voltage V 1.8 Inductive load switching time and energy ton tc(on) toff tc(off) trr Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching losses Eoff Turn-off switching losses VDD = 300 V, VCC = Vboot = 15 V, VIN(1) = 0 ÷ 5 V, IC = 7 A (see Figure 5) - 270 - - 130 - - 520 - - 140 - - 130 - - 150 - - 110 - ns µJ 1. Applied between HINi, LINi and GND for i = U, V, W (LIN inputs are active-low). Note: tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. DocID018534 Rev 5 7/19 19 Electrical characteristics STGIPS14K60T Figure 3. Switching time test circuit INPUT BUS BOOT /Lin VBOOT>VCC +5V /SD HVG RSD L Hin OUT VCC Vcc IC DT LVG GND CP+ VCE 0 1 AM17167v1 Figure 4. Switching time definition 100% IC 100% IC t rr IC VCE VIN VIN t ON t C(ON) VIN(ON) 10% IC 90% IC 10% VCE (a) turn-on Note: 8/19 VCE IC t OFF VIN(OFF) t C(OFF) 10% VCE (b) turn-off 10% IC AM09223V1 Figure 4: Switching time definition refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. DocID018534 Rev 5 STGIPS14K60T 3.1 Electrical characteristics Control part Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn OFF threshold 10 10.5 11 V VCC_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 10 V SD = 5 V; LIN = 5 V; HIN = 0 450 µA Iqcc Quiescent current VCC = 15 V SD = 5 V; LIN = 5 V HIN = 0 3.5 mA Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current VBS < 9 V SD = 5 V; LIN and HIN = 5 V 70 110 µA IQBS VBS quiescent current VBS = 15 V SD = 5 V; LIN and HIN = 5 V 200 300 µA Bootstrap driver on resistance LVG ON 120 VBS_hys RDS(on) Parameter Test conditions Ω Table 10. Logic inputs (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Vil Low logic level voltage 0.8 1.1 V Vih High logic level voltage 1.9 2.25 V 260 µA 1 µA 20 µA 1 µA 300 µA 3 µA IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V ISDl SD logic “1” input bias current SD = 0 V Dt Dead time see Figure 9 DocID018534 Rev 5 110 3 30 175 6 120 600 ns 9/19 19 Electrical characteristics STGIPS14K60T Table 11. Shut down characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Shut down to high / low side driver propagation delay tsd VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V Min. Typ. Max. Unit 50 125 200 ns Table 12. Truth table Logic input (VI) Output Condition SD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X X L L Interlocking half-bridge tri-state H L H L L 0 ‘’logic state” half-bridge tri-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: X: don’t care  931 90RGXODWLRQLQGH[  3) 7 M ƒ&I6,1( +]  Figure 6. Maximum IC(RMS) current vs. fSINE (1) ,F506 >$@ , F506 >$@ Figure 5. Maximum IC(RMS) current vs. switching frequency (1)   931 90RGXODWLRQLQGH[  3) 7M ƒ&7F ƒ&   7F ƒ&     IVZ N+] 7F ƒ&  IVZ N+]  IVZ N+]           I VZ>N+]@ 1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. 10/19 DocID018534 Rev 5     I 6,1( >+]@ STGIPS14K60T 3.1.1 Electrical characteristics NTC thermistor Table 13. NTC thermistor Symbol Parameter Test conditions Min. Typ. Max. Unit. R25 Resistance T = 25°C 4.7 kΩ R125 Resistance T = 125°C 160 Ω B B-constant T = 25°C to 85°C 3950 K T Operating temperature -40 150 °C Equation 1: resistance variation vs. temperature R ( T ) = R 25 ⋅ e 1 1 B  --- – ----------  T 298 Where T are temperatures in Kelvins Figure 7. NTC resistance vs. temperature AM17168v1 NTC [kΩ] 180 160 140 120 100 80 MAX. 60 CENTER 40 20 MIN. 0 -40 -20 0 20 40 60 80 100 120 140 (°C) Figure 8. NTC resistance vs. temperature (zoom) AM17169v1 NTC [kΩ] 1.8 1.6 1.4 1.2 1.0 0.8 MAX. 0.6 CENTER 0.4 MIN. 0.2 0.0 50 60 70 80 90 100 110 120 130 140 (°C) DocID018534 Rev 5 11/19 19 Electrical characteristics 3.2 STGIPS14K60T Waveform definitions Figure 9. Dead time and interlocking waveform definitions G LOC K CKIN HIN LVG INTE R INTE RLO CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected together and driven by just one control signal 12/19 DocID018534 Rev 5 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) STGIPS14K60T 4 Applications information Applications information Figure 10. Typical application circuit AM09321v2 DocID018534 Rev 5 13/19 19 Applications information 4.1 STGIPS14K60T Recommendations • Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. • Input signal /LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. • To prevent the input signals oscillation, the wiring of each input should be as short as possible. • By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. • Each capacitor should be located as nearby the pins of IPM as possible. • Low inductance shunt resistors should be used for phase leg current sensing. • Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. • The SD signal should be pulled up to 5 V / 3.3 V with an external resistor. Table 14. Recommended operating conditions Value Symbol Parameter Conditions Unit Min. VPN Supply Voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent Arm-short For each input signal 1 fPWM PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C TC Note: 14/19 Case operation temperature For further details, refer to AN3338. DocID018534 Rev 5 13.5 Typ. Max. 300 400 V 15 18 V 18 V µs 20 kHz 100 °C STGIPS14K60T 5 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. 5.1 SDIP-25L package information Figure 11. SDIP-25L package outline B DocID018534 Rev 5 15/19 19 Package information STGIPS14K60T Table 15. SDIP-25L mechanical data mm Dim. 16/19 Min. Typ. Max. A 43.90 44.40 44.90 A1 1.15 1.35 1.55 A2 1.40 1.60 1.80 A3 38.90 39.40 39.90 B 21.50 22.00 22.50 B1 11.25 11.85 12.45 B2 24.83 25.23 25.63 C 5.00 5.40 6.00 C1 6.50 7.00 7.50 C2 11.20 11.70 12.20 C3 2.90 3.00 3.10 e 2.15 2.35 2.55 e1 3.40 3.60 3.80 e2 4.50 4.70 4.90 e3 6.30 6.50 6.70 D 33.30 D1 5.55 E 11.20 E1 1.40 F 0.85 1.00 1.15 F1 0.35 0.50 0.65 R 1.55 1.75 1.95 T 0.45 0.55 0.65 V 0° 6° DocID018534 Rev 5 STGIPS14K60T Packing information 8123127_E AM10488v1 Figure 12. SDIP-25L packing information (dimensions are in mm.) Base quantity: 11 pcs Bulk quantity: 132 pcs 5.2 Package information DocID018534 Rev 5 17/19 19 Revision history 6 STGIPS14K60T Revision history Table 16. Document revision history 18/19 Date Revision Changes 07-Mar-2011 1 Initial release. 14-Sep-2011 2 Update Section 3.1.1 on page 11. 28-Aug-2012 3 Modified: Min. and Max. value Table 4 on page 5. Updated: Table 15 on page 15, Figure 11 on page 15, Figure 12 on page 17. Added: Figure 13 on page 18. 15-May-2013 4 Modified: description pin 15 Table 2 on page 4 and VSD parameter Table 4 on page 5. 15-Apr-2015 5 Text edits and formatting changes throughout document Updated Figure 2: Pin layout (bottom view) Updated Section 5: Package information DocID018534 Rev 5 STGIPS14K60T IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID018534 Rev 5 19/19 19