STGIPS20K60

STGIPS20K60 IGBT intelligent power module (IPM) 18 A, 600 V, DBC isolated SDIP-25L molded Features ■ 18 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes ■ 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down / pull up resistors ■ Internal bootstrap diode ■ Interlocking function ■ VCE(sat) negative temperature coefficient ■ Short-circuit rugged IGBTs ■ Undervoltage lockout ■ Smart shutdown function ■ Comparator for fault protection against over temperature and overcurrent ■ DBC fully isolated package ■ Isolation rating of 2500 Vrms/min SDIP-25L technology. Please refer to dedicated technical note TN0107 for mounting instructions. Applications ■ 3-phase inverters for motor drives ■ Home appliances, such as washing machines, refrigerators, air conditioners Description The STGIPS20K60 intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It mainly targets low power inverters for applications such as home appliances and air conditioners. It combines ST proprietary control ICs with the most advanced short circuit rugged IGBT system Table 1. Device summary Order code Marking Package Packaging STGIPS20K60 GIPS20K60 SDIP-25L Tube September 2010 Doc ID 16098 Rev 3 1/19 www.st.com 19 Contents STGIPS20K60 Contents 1 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 16098 Rev 3 STGIPS20K60 1 Internal block diagram and pin configuration Internal block diagram and pin configuration Figure 1. Internal block diagram Pin 1 Pin 25 OUT U P VBOOT U LIN Vboot LIN-U SD/OD HVG HIN-U HIN VCC OUT U VCC DT LVG CP+ NU GND OUT V VBOOT V P LIN GND Vboot SD/OD HVG LIN-V HIN HIN-V VCC OUT V DT LVG CP+ NV GND OUT W VBOOT W P LIN Vboot LIN-W SD/OD HVG HIN-W HIN SD/OD VCC CIN OUT W DT LVG Pin 16 CP+ NW GND Pin 17 AM05002v1 Doc ID 16098 Rev 3 3/19 Internal block diagram and pin configuration Table 2. Pin description Pin n° Symbol 1 OUTU High-side reference output for U phase 2 VbootU Bootstrap voltage for U phase 3 LINU Low-side logic input for U phase 4 HINU High-side logic input for U phase 5 VCC Low voltage power supply 6 OUTV High-side reference output for V phase 7 Vboot V Bootstrap voltage for V phase 8 GND Ground 9 LINV Low-side logic input for V phase 10 HINV High-side logic input for V phase 11 OUTW High-side reference output for W phase 12 Vboot W Bootstrap voltage for W phase 13 LINW Low-side logic input for W phase 14 HINW High-side logic input for W phase 15 SD / OD 16 CIN Comparator input 17 NW Negative DC input for W phase 18 W W phase output 19 P Positive DC input 20 NV Negative DC input for V phase 21 V V phase output 22 P Positive DC input 23 NU Negative DC input for U phase 24 U U phase output 25 P Positive DC input Figure 2. 4/19 STGIPS20K60 Description Shutdown logic input (active low) / open-drain (comparator output) Pin layout (bottom view) Doc ID 16098 Rev 3 STGIPS20K60 Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol Parameter Value Unit VPN Supply voltage applied between P - NU, NV, NW 450 V VPN(surge) Supply voltage (surge) applied between P - NU, NV, NW 500 V VCES Collector emitter voltage (VIN(1) = 0) 600 V ± IC(2) Each IGBT continuous collector current at TC = 25°C 18 A Each IGBT pulsed collector current 40 A PTOT Each IGBT total dissipation at TC = 25°C 52 W tscw Short circuit withstand time, VCE = 0.5 V(BR)CES TJ = 125 °C, VCC = Vboot= 15 V, VIN (1)= 0 ÷ 5 V 5 µs Value Unit Vboot - 21 to Vboot + 0.3 V ± ICP (3) 1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula: T j ( max ) – T C I C ( T C ) = ------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 3. Pulse width limited by max junction temperature Table 4. Control part Symbol Parameter VOUT Output voltage applied between OUTU, OUTV, OUTW - GND VCC Low voltage power supply -0.3 to +21 V VCIN Comparator input voltage -0.3 to VCC +0.3 V Vboot Bootstrap voltage applied between Vboot i - OUTi for i = U, V, W -0.3 to 620 V Logic input voltage applied between HIN, LIN and GND -0.3 to 15 V Open drain voltage -0.3 to 15 V 50 V/ns VIN VSD/OD dVOUT/dt Allowed output slew rate Doc ID 16098 Rev 3 5/19 Electrical ratings Table 5. STGIPS20K60 Total system Symbol Parameter Value Unit 2500 V VISO Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 sec.) Tj (1) Operating junction temperature -40 to 150 °C Module case operation temperature -40 to 125 °C TC 1. The maximum junction temperature rating of the power chips integrated within the SDIP module is 150°C (@TC ≤ 100°C). To ensure safe operation of the SDIP module, the average junction temperature should be limited to Tj(avg) ≤ 125°C (@TC ≤ 100°C) 2.2 Thermal data Table 6. Symbol RthJC 6/19 Thermal data Parameter Value Unit Thermal resistance junction-case single IGBT 2.4 °C/W Thermal resistance junction-case single diode 5 °C/W Doc ID 16098 Rev 3 STGIPS20K60 3 Electrical characteristics Electrical characteristics (TJ = 25 °C unless otherwise specified) Table 7. Inverter part Value Symbol VCE(sat) ICES VF Parameter Test conditions Unit Min. Typ. Max. VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 12 A - 2.2 2.75 VCC = Vboot = 15 V, VIN(1)= 0 ÷ 5 V, IC = 12 A, TJ = 125 °C - Collector-cut off current (VIN(1)= 0 “logic state”) VCE = 600 V, VCC = VBoot = 15 V - 100 µA Diode forward voltage VIN(1) = 0 “logic state”, IC = 12 A - 3.8 V Collector-emitter saturation voltage V 1.8 Inductive load switching time and energy ton tc(on) toff tc(off) trr Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching losses Eoff Turn-off switching losses VPN = 300 V, VCC = Vboot = 15 V, VIN(1) = 0 ÷ 5 V, IC = 12 A (see Figure 3) - 300 - - 150 - - 730 - - 170 - - 60 - - 290 - - 250 - ns µJ 1. Applied between HINi, LINi and GND for i = U, V, W. (LIN inputs are active-low). Note: tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. Doc ID 16098 Rev 3 7/19 Electrical characteristics STGIPS20K60 Figure 3. Switching time test circuit Figure 4. Switching time definition Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. 8/19 Doc ID 16098 Rev 3 STGIPS20K60 Electrical characteristics 3.1 Control part Table 8. Low voltage power supply Symbol Min. Typ. Max. Unit Vcc UV hysteresis 1.2 1.5 1.8 V Vcc_thON Vcc UV turn ON threshold 11.5 12 12.5 V Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 11 V Vcc_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 450 µA Iqcc Quiescent current Vcc = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 3.5 mA Vref Internal comparator (CIN) reference voltage 0.58 V Table 9. Bootstrapped voltage Symbol Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 10.6 11.5 12.4 V VBS_thOFF VBS UV turn OFF threshold 9.1 10 10.9 V IQBSU Undervoltage VBS quiescent current VBS = 10 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 70 110 µA IQBS VBS quiescent current VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 150 210 µA Bootstrap driver on resistance LVG ON 120 RDS(on) Table 10. Test conditions 0.54 Min. VBS_hys Parameter 0.5 Ω Logic inputs Symbol Parameter Vil Low logic level voltage Vih High logic level voltage Test conditions Min. Typ. Max. Unit 0.8 V 2.25 IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V ISDl SD logic “1” input bias current SD = 0 V Dt Dead time see Figure 7 Doc ID 16098 Rev 3 110 3 30 V 175 6 120 600 260 µA 1 µA 20 µA 1 µA 300 µA 3 µA ns 9/19 Electrical characteristics Table 11. STGIPS20K60 Sense comparator characteristics (VCC = 15 V) Symbol Parameter Test conditions Min. Typ. Max. Unit Iib Input bias current VCP+ = 1 V - 3 µA Vol Open-drain low-level output voltage Iod = - 3 mA - 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor - 90 130 ns SR Slew rate CL = 180 pF; Rpu = 5 kΩ - 60 tsd Shut down to high / low side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V 50 125 tisd Comparator triggering to high / low side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CINi td_comp Table 12. V/µsec 200 ns 50 200 250 Truth table Logic input (VI) Output Condition SD/OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X X L L Interlocking half-bridge tri-state H L H L L 0 ‘’logic state” half-bridge tri-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: 10/19 X: don’t care Doc ID 16098 Rev 3 STGIPS20K60 Figure 5. Electrical characteristics Maximum IC(RMS) current vs. switching frequency (1) Figure 6. Maximum IC(RMS) current vs. fSINE (1) AM07841v1 26 AM07842v1 16 24 15 VPN = 300 V, Modulation index = 0.8, 22 14 PF = 0.6, Tj = 150 °C, TC = 100 °C TC = 80 °C 13 I c(RMS) [A] I c(RMS) [A] 20 18 TC = 100 °C 16 12 11 fSW = 12 kHz 14 10 VPN = 300 V, Modulation index = 0.8, PF = 0.6, Tj = 150 °C, fSINE = 60 Hz 12 fSW = 16 kHz 9 fSW = 20 kHz 10 4 8 12 16 20 8 1 fSW [kHz] 10 f SINE [Hz] 100 1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c. Doc ID 16098 Rev 3 11/19 Electrical characteristics 3.2 STGIPS20K60 Waveforms definitions Figure 7. Dead time and interlocking waveforms definitions INTE RLO CK ING HIN INTE RLO CK CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected together and driven by just one control signal 12/19 Doc ID 16098 Rev 3 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) STGIPS20K60 4 Smart shutdown function Smart shutdown function The STGIPS20K60 integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. Figure 8. Smart shutdown timing waveforms comp Vref CP+ PROTECTION HIN/LIN HVG/LVG SD/OD upper threshold lower threshold 1 2 open drain gate (internal) real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold TIME CONSTANTS 1 = (RON_OD // RSD) CSD 2 = RSD CSD SHUT DOWN CIRCUIT VBIAS RSD SD/OD FROM/TO CONTROLLER CSD RON_OD SMART SD LOGIC Pls refer to Table 11 for internal propagation delay time details. Doc ID 16098 Rev 3 13/19 14/19 3.3V/5V Line Doc ID 16098 Rev 3 Csd Rsd Cbw Cbv CIN SD/OD HIN-W LIN-W VBOOT W OUT W HIN-V LIN-V GND VBOOT V OUT V VCC Rdt Cvcc Rdt Cvcc Rdt Cvcc Cdt Cdt Cdt OUT HIN OUT HIN OUT HIN GND DT CP+ LVG HVG VCC Vboot SD/OD CP+ LIN GND DT LVG HVG VCC Vboot SD/OD CP+ LIN GND DT LVG HVG SD/OD VCC Vboot LIN Rg Rg Rg Rg Rg Rg T6 T5 T4 T3 T2 T1 D6 D5 D4 D3 D2 D1 C R Nw W Nv V Nu U P Rshunt M + VDC Figure 9. HIN-U LIN-U VBOOT U OUT U 5 VCC Cbu Applications information STGIPS20K60 Applications information Typical application circuit CONTROLLER AM05001v2 STGIPS20K60 5.1 Applications information Recommendations ● Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. ● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. ● By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. ● Each capacitor should be located as nearby the pins of IPM as possible. ● Low inductance shunt resistors should be used for phase leg current sensing. ● Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Table 13. Recommended operating conditions Value Symbol Parameter Conditions Unit Min. VPN Supply Voltage Applied between P-Nu,Nv,Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage tdead fPWM 13.5 Applied between VBOOTi-OUTi for i=U,V,W 13 Blanking time to prevent Arm-short For each input signal 1 PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C Doc ID 16098 Rev 3 Typ. Max. 300 400 V 15 18 V 18 V µs 20 kHz 15/19 Package mechanical data 6 STGIPS20K60 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 14. SDIP-25L package mechanical data (mm.) Dim. Min. 16/19 Typ. Max. A 44 44.8 A1 0.95 1.75 A2 1.2 2 A3 39 39.8 B 21.6 22.4 B1 11.45 12.25 B2 24.83 C 5 5.8 C1 6.4 7.4 C2 11.1 12.1 e 1.95 2.35 2.75 e1 3.2 3.6 4 e2 4.3 4.7 5.1 e3 6.1 6.5 6.9 F 0.8 1.0 1.2 F1 0.3 0.5 0.7 R 1.35 T 0.4 Doc ID 16098 Rev 3 25.22 25.63 2.15 0.55 0.7 STGIPS20K60 Package mechanical data ' & ( Figure 10. SDIP-25L package dimensions 8154676 revF Doc ID 16098 Rev 3 17/19 Revision history 7 STGIPS20K60 Revision history Table 15. 18/19 Document revision history Date Revision Changes 10-Aug-2009 1 Initial release 01-Jul-2010 2 Document status promoted from preliminary to datasheet. Updated package mechanical data (Section 6: Package mechanical data). Minor text changes to improve readability. 23-Sep-2010 3 Updated: Table 3, 5, 10 and Table 11. Modified: Figure 5 and Figure 6. Doc ID 16098 Rev 3 STGIPS20K60 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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