STGIPS40W60L1

STGIPS40W60L1 SLLIMM™ (small low-loss intelligent molded module) IPM, single phase - 40 A, 600 V ultra fast IGBT Datasheet − production data Features ■ IPM 40 A, 600 V single phase IGBT including control ICs for gate driving and free-wheeling diodes ■ Very high switching speed IGBTs ■ VCE(sat) negative temperature coefficient ■ 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down / pull up resistors ■ Undervoltage lockout ■ Internal bootstrap diode ■ Dead time and interlocking function ■ Smart shutdown function ■ Comparator for fault protection against over temperature and overcurrent Description ■ Op amp for advanced current sensing ■ DBC substrate leading to low thermal resistance ■ Isolation rating of 2500 Vrms/min ■ 4.7 kΩ NTC UL recognized for temperature control ■ UL Recognized : UL1557 file E81734 This intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It targets high frequency converters. It combines ST proprietary control ICs with the most advanced IGBT and diode technologies tailored to high switching frequency operation. SLLIMM™ is a trademark of STMicroelectronics. SDIP-22L Applications ■ Power factor correction for compressors Table 1. Device summary Order code Marking Package Packaging STGIPS40W60L1 GIPS40W60L1 SDIP-22L Tube August 2012 This is information on a product in full production. Doc ID 018866 Rev 3 1/21 www.st.com 21 Contents STGIPS40W60L1 Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 3.2 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 Dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 Doc ID 018866 Rev 3 Doc ID 018866 Rev 3 Pin16: GND Pin15: GND Pin14: CIN Pin13: VCC Pin12: OP+ Pin11: OPOUT Pin10: OP- Pin9: DT Pin8: HIN Pin7: /SD Pin6: /LIN Pin5: T2 Pin4: T1 Pin3: NC Vboot LVG OUT GND OP+ OPOUT CP+ OP- DT VCC HIN SD/OD HVG LIN Pin17: N Pin18: N Pin19: PHASE Pin20: PHASE Pin21: P Pin22: P Figure 1. Pin2: VBOOT 1 Pin1: OUT STGIPS40W60L1 Internal schematic diagram and pin configuration Internal schematic diagram and pin configuration Internal schematic diagram AM09386v2 3/21 Internal schematic diagram and pin configuration Table 2. Pin description Pin Symbol 1 OUTPHASE 2 Vboot 3 NC Not connected 4 T1 NTC thermistor terminal 1 5 T2 NTC thermistor terminal 2 6 LIN Low side logic input 7 SD/OD 8 HIN High side logic input 9 DT Dead time setting 10 OP- Op amp inverting input 11 OPOUT 12 OP+ Op amp non inverting input 13 VCC Low voltage power supply 14 CIN Comparator input 15 GND Ground 16 GND Ground 17 N Negative DC input 18 N Negative DC input 19 PHASE Phase output 20 PHASE Phase output 21 P Positive DC input 22 P Positive DC input Figure 2. STGIPS40W60L1 Description PHASE reference output Bootstrap voltage Shutdown logic input (active low) / open drain (comparator output) Op amp output Pin layout (bottom view) Marking area AM06017v1 4/21 Doc ID 018866 Rev 3 STGIPS40W60L1 Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 3. Inverter part Symbol Parameter Value Unit VCES Each IGBT collector emitter voltage (VIN = 0) 600 V ± IC(1) Each IGBT continuous collector current at TC = 25°C 40 A Each IGBT pulsed collector current 80 A Each IGBT total dissipation at TC = 25°C 100 W ± ICP (2) PTOT 1. Calculated according to the iterative formula: Tj ( max ) – TC IC ( T C ) = ------------------------------------------------------------------------------------------------------R thj – c × V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) ) 2. Pulse width limited by max junction temperature Table 4. Control part Symbol Parameter Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied between OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ OPAMP non-inverting input - 0.3 VCC + 0.3 V Vop- OPAMP inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied between HIN, LIN and GND - 0.3 15 V Open drain voltage - 0.3 15 V 50 V/ns VIN VSD/OD dVOUT/dt Table 5. Symbol VISO Allowed output slew rate Total system Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 sec.) Value Unit 2500 V TJ Power chips operating junction temperature -40 to 150 °C TC Module case operation temperature -40 to 125 °C Doc ID 018866 Rev 3 5/21 Electrical ratings 2.2 STGIPS40W60L1 Thermal data Table 6. Thermal data Symbol Parameter RthJC Figure 3. Value Unit Thermal resistance junction-case single IGBT 1.25 °C/W Thermal resistance junction-case single diode 2.5 °C/W Transient thermal impedance IGBT/diode - inverter AM09385v1 10 Zthj-c [K/W] 1 Diode IGBT 0.1 0.01 1.E-04 1.E-03 1.E-02 1.E-01 time [s] 6/21 Doc ID 018866 Rev 3 1.E+00 1.E+01 1.E+02 STGIPS40W60L1 3 Electrical characteristics Electrical characteristics TJ = 25 °C unless otherwise specified. Table 7. Inverter part Value Symbol VCE(sat) ICES VF Parameter Test conditions Unit Min. Typ. Max. VCC = Vboot = 15 V, VIN = 1 "logic state", IC = 30 A - 2.0 2.5 VCC = Vboot = 15 V, VIN = 1 "logic state", IC = 30 A, TJ = 125 °C - 1.7 Collector-cut off current (VIN = 0 "logic state") VCE = 550 V, VCC = VBoot = 15 V, - 500 µA Diode forward voltage VIN = 0 "logic state", IF = 30A - 2.5 V Collector-emitter saturation voltage V Switching on/off (inductive load) (1) ton tc(on) toff tc(off) trr Turn-on time - 410 - Crossover time (on) - 80 - - 320 - - 125 - - 115 - Turn-off time Crossover time (off) Reverse recovery time VDD = 410 V, VCC = Vboot = 15 V, VIN = 1 "logic state" (see Table 13) IC = 30 A (see Figure 4 and 5) Eon Turn-on switching losses - 585 - Eoff Turn-off switching losses - 600 - - 2500 - - 550 - - 110 - - 420 - - 140 - - 150 - - 930 - - 780 - - 2100 - di/dt(on) ton tc(on) toff tc(off) trr µJ Rate of rise of on-state current VDD = 410 V, VCC = Vboot = 15 V, VIN = 1 "logic state" (see Table 13), IC = 80 A (see Figure 4 and 5) Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Eon Turn-on switching losses Eoff Turn-off switching losses di/dt(on) ns VDD = 410 V, VCC = Vboot = 15 V, VIN = 1 "logic state" (see Table 13) IC = 30 A, TJ = 125 °C (see Figure 4 and 5) A/µs ns µJ Rate of rise of on-state current VDD = 410 V, VCC = Vboot = 15 V, VIN = 1 "logic state" (see Table 13) IC = 80 A, TJ = 125 °C (see Figure 4 and 5) A/µs 1. tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition. Parameter values take into account a 20 nH stray inductance. Doc ID 018866 Rev 3 7/21 Electrical characteristics STGIPS40W60L1 Figure 4. Switching time test circuit Figure 5. Switching time definition (1) 100% IC 100% IC t rr IC VCE VCE IC VIN VIN t ON t OFF t C(OFF) t C(ON) VIN(ON) 10% IC 90% IC 10% VCE (a) turn-on VIN(OFF) 10% VCE (b) turn-off 10% IC AM09223V1 1. “Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity must be inverted for turn-on and turn-off. 8/21 Doc ID 018866 Rev 3 STGIPS40W60L1 Electrical characteristics 3.1 Control part Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified) Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn OFF threshold 10 10.5 11 V VCC_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 200 µA Iqcc Quiescent current VCC = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 1 mA Vref Internal reference voltage 0.58 V Table 9. Symbol 0.5 0.54 Bootstrapped voltage (VCC = 15 V unless otherwise specified) Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold 10.6 11.5 12.4 V VBS_thOFF VBS UV turn OFF threshold 9.1 10 10.9 V IQBSU Undervoltage VBS quiescent current VBS < 9 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 70 110 µA IQBS VBS quiescent current VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 150 210 µA Bootstrap driver on resistance LVG ON 120 VBS_hys RDS(on) Table 10. Symbol Parameter Test conditions Ω Logic inputs (VCC = 15 V unless otherwise specified) Parameter Vil Low logic level voltage Vih High logic level voltage Test conditions Min. Typ. Max. Unit 0.8 V 2.25 IHINh HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “1” input bias current LIN = 0 V ILINh LIN logic “0” input bias current LIN = 15 V ISDh SD logic “0” input bias current SD = 15 V ISDl SD logic “1” input bias current SD = 0 V Doc ID 018866 Rev 3 110 3 10 V 175 6 40 260 µA 1 µA 20 µA 1 µA 100 µA 1 µA 9/21 Electrical characteristics Table 11. STGIPS40W60L1 Op amp characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Input bias current (1) Test condition Min Typ Max Unit 6 mV 4 40 nA 100 200 nA Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V Vicm Input common mode voltage range VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = + 1; Vo = 0 V 16 30 mA Sink, Vid = - 1; Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/μs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Io SR Output short circuit current 0 V 75 150 mV 1. The direction of input current is out of the IC. Table 12. Sense comparator characteristics (VCC = 15 V unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit Iib Input bias current VCP+ = 1 V - 1 µA Vol Open-drain low-level output voltage Iod = 3 mA - 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor - 90 130 ns SR Slew rate CL = 180 pF; Rpu = 5 kΩ - 60 tsd Shutdown to high / low side driver propagation delay VOUT = 0, Vboot = VCC, VIN = 0 to 3.3 V 50 125 tisd Comparator triggering to high / low side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CINi td_comp 10/21 Doc ID 018866 Rev 3 V/µsec 200 ns 50 200 250 STGIPS40W60L1 Table 13. Electrical characteristics Truth table Logic input (VI) Output Condition SD/OD LIN HIN LVG HVG Shutdown enable half-bridge tri-state L X X L L Interlocking half-bridge tri-state H L H L L 0 ‘’logic state” half-bridge tri-state H H L L L 1 “logic state” low side direct driving H L L H L 1 “logic state” high side direct driving H H H L H Note: X: don’t care Doc ID 018866 Rev 3 11/21 Electrical characteristics 3.1.1 STGIPS40W60L1 NTC thermistor Table 14. NTC thermistor Symbol Parameter Test conditions Min. R25 Resistance TC = 25°C 4.7 kΩ R125 Resistance TC = 125°C 160 Ω B B-constant TC = 25°C 3950 K T Operating temperature -40 Equation 1: resistance variation vs. temperature R ( T ) = R 25 ⋅ e 1 1 B ⎛⎝ --- – ----------⎞⎠ T 298 Where T are temperatures in Kelvins Figure 6. NTC resistance vs. temperature AM07843v1 R (kΩ) 100 10 1 0.1 0.01 -50 12/21 Typ. Max. Unit. 0 50 Doc ID 018866 Rev 3 100 T (°C) 150 °C STGIPS40W60L1 Dead time Figure 7. Dead time and interlocking waveforms definitions INTE RLO CK ING HIN INTE RLO CK CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME ING LIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected together and driven by just one control signal Figure 8. Typical dead time vs. DT resistor value 3.5 3 2.5 2 DT (µs) 3.1.2 Electrical characteristics 1.5 1 0.5 0 0 50 100 150 200 250 300 Rdt (kOhm) AM06020v1 Doc ID 018866 Rev 3 13/21 Electrical characteristics 3.2 STGIPS40W60L1 Recommendations ● Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. ● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. ● By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. ● Each capacitor should be located as nearby the pins of IPM as possible. ● Low inductance shunt resistors should be used for phase leg current sensing. ● Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ● The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). ● When setting the maximum voltage to be applied between P-N, the internal stray inductance and the maximum di/dt should be considered. Due to both internal and layout stray inductances, the di/dt results in a voltage surges between the DC-link capacitor and the switches during commutations. ● Suggested control supply voltage (VCC): from 13.5 V to 18 V ● Suggested high side bias voltage (VBS between VBOOT and PHASE): from 13 V to 18 V Table 15. Recommended operating conditions Value Symbol Parameter Conditions Unit Min. VPN Supply voltage Applied between P-Nu, Nv, Nw VCC Control supply voltage Applied between VCC-GND VBS High side bias voltage Applied between VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent Arm-short For each input signal 1 fPWM PWM input signal -40°C < Tc < 100°C -40°C < Tj < 125°C TC Case operation temperature For further details refer to AN3338. 14/21 Doc ID 018866 Rev 3 13.5 Typ. Max. 300 400 V 15 18 V 18 V µs 20 kHz 100 °C STGIPS40W60L1 4 Smart shutdown function Smart shutdown function The STGIPS40W60L1 integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple overcurrent protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. Figure 9. Smart shutdown timing waveforms comp Vref CP+ PROTECTION HIN/LIN HVG/LVG SD/OD upper threshold lower threshold 1 2 open drain gate (internal) real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold TIME CONSTANTS 1 = (RON_OD // RSD) CSD 2 = RSD CSD SHUT DOWN CIRCUIT VBIAS RSD FROM/TO CONTROLLER SD/OD CSD RON_OD SMART SD LOGIC Pls refer to Table 12 for internal propagation delay time details. Doc ID 018866 Rev 3 15/21 Package mechanical data 5 STGIPS40W60L1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-22L package mechanical data mm. Dim. 16/21 Min. Typ. Max. A 43.90 44.40 44.90 A1 1.15 1.35 1.55 A2 1.40 1.60 1.80 A3 38.90 39.40 39.90 B 21.50 22.00 22.50 B1 11.25 11.85 12.45 B2 24.83 25.23 25.63 C 5.00 5.40 6.00 C1 6.50 7.00 7.50 C2 11.20 11.70 12.20 e 2.15 2.35 2.55 e1 3.40 3.60 3.80 e2 4.50 4.70 4.90 e3 15.70 15.90 16.10 e4 6.30 6.50 6.70 e5 9.20 9.40 9.60 D 33.20 D1 5.60 E 10.20 E1 0.40 F 0.85 1.00 1.15 F1 0.35 0.50 0.65 R 1.55 1.75 1.95 T 0.45 0.55 0.65 V 0° Doc ID 018866 Rev 3 6° STGIPS40W60L1 Package mechanical data Figure 10. SDIP-22L package drawing (dimensions are in mm.) 8229874_D Doc ID 018866 Rev 3 17/21 Package mechanical data STGIPS40W60L1 Base quantity: 11 pcs Bulk quantity: 132 pcs 8123127_E AM10488v1 Figure 11. SDIP-22L shipping tube (dimensions are in mm.) 18/21 Doc ID 018866 Rev 3 STGIPS40W60L1 Package mechanical data Base quantity: 11 pcs Bulk quantity: 132 pcs 8123127_E ANTIS TATIC S 03 PVC AM10487v1 Figure 12. SDIP-22L shipping tube type B (dimensions are in mm.) Doc ID 018866 Rev 3 19/21 Revision history 6 Revision history Table 17. Document revision history Date Revision 14-Jun-2011 1 Initial release. 24-Jan-2012 2 Added: Figure 11 on page 18. Updated: Figure 10 on page 17. 3 Document status promoted from preliminary data to production data. Added: feature Comparator for fault protection against over temperature and overcurrent on page 1. Modified: Min. and Max. value Table 4 on page 5. 28-Aug-2012 20/21 STGIPS40W60L1 Changes Doc ID 018866 Rev 3 STGIPS40W60L1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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