STH180N10F3-6

STH180N10F3-6 N-channel 100 V, 3.9 mΩ typ.,180 A, STripFET™ F3 Power MOSFET in H²PAK-6 package Datasheet - production data Features TAB VDS RDS(on) max. ID STH180N10F3-6 100 V 4.5 mΩ 180 A u d o 7 1 H2PAK-6 Figure 1: Internal schematic diagram ) s ( ct ) s ( ct Order code   Low on-resistence RDS(on) 100% avalanche tested  Switching applications r P Applications e t e l o s Description b -O u d o Pr eS(2,3,4,5,6,7) t e ol This device is an N-channel Power MOSFET developed using STripFET™ F3 technology. It is designed to minimize on-resistance and gate charge to provide superior switching performance. Table 1: Device summary Order code Marking Package Packing STH180N10F3-6 180N10F3 H2PAK-6 Tape and reel s b O November 2014 DocID022347 Rev 4 This is information on a product in full production. 1/15 www.st.com Contents STH180N10F3-6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 H2PAK-6 package information ........................................................... 9 4.2 Packing information......................................................................... 12 ) s ( ct 5 Revision history ............................................................................ 14 u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/15 DocID022347 Rev 4 STH180N10F3-6 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Drain-source voltage 100 V VGS Gate-source voltage ± 20 V (1) ID Drain current (continuous) at TC = 25 °C 180 A (1) ID Drain current (continuous) at TC = 100 °C 120 A Drain current (pulsed) 720 A Total dissipation at TC = 25 °C 315 W Derating factor 2.1 Peak diode recovery voltage slope 20 EAS Single pulse avalanche energy 350 TJ Operating junction temperature Tstg Storage temperature PTOT dv/dt (3) -55 to 175 e t e ol Notes: (2) (3) Unit VDS (2) IDM (1) Value Current limited by package Pulse width limited by safe operating area Starting TJ = 25 °C, ID = 80, VDD = 50 V ) (s ) s ( ct W/ºC V/ns Pr u d o mJ °C °C s b O Table 3: Thermal resistance Symbol Rthj-case Rthj-pcb Notes: (1) (1) Parameter ct Thermal resistance junction-case du Thermal resistance junction-pcb Value Unit 0.48 °C/W 35 °C/W o r P When mounted on FR-4 board of 1 inch², 2 oz Cu e t e ol s b O DocID022347 Rev 4 3/15 Electrical characteristics 2 STH180N10F3-6 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4: On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage (VGS= 0) ID = 250 µA VDS = 100 V; TC = 125 °C 100 µA Gate body leakage current (VDS = 0) VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 60 A Input capacitance Coss Output capacitance Crss Reverse transfer capacitance (s) Qgs Gate-source charge Qgd Gate-drain charge e t e ol ct td(on) tr td(off) tf du o r P Parameter Turn-on delay time Rise time Turn-off delay time Fall time r P e -O ) s ( ct u d o Min. VDS = 25 V, f = 1 MHz, VGS = 0 Total gate charge Symbol 4/15 o s b 2 3.9 let Test conditions Qg V µA IGSS Ciss Unit 10 IDSS Parameter Max. VDS = 100 V Zero gate voltage drain current (VGS = 0) Symbol Typ. 100 Table 5: Dynamic s b O Min. Typ. ±200 nA 4 V 4.5 mΩ Max. Unit 6665 pF 786 pF 49 - VDD = 50 V, ID = 120 A VGS = 10 V See Figure 14: "Gate charge test circuit" pF - 114.6 nC 38.8 nC 31.9 nC Table 6: Switching times Test conditions VDD = 50 V, ID = 60 A, RG = 4.7 Ω, VGS= 10 V See Figure 13: "Switching times test circuit for resistive load" DocID022347 Rev 4 Min. Typ. Max. 25.6 ns 97.1 - 99.9 6.9 Unit ns - ns ns STH180N10F3-6 Electrical characteristics Table 7: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Source-drain current (1) ISDM Source-drain current (pulsed) (2) VSD Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 120 A, VGS = 0 ISD = 120 A, di/dt = 100 A/µs, VDD = 80 V, Tj = 150 °C - Max. Unit 180 A 720 A 1.5 V 83.4 ns 295.7 nC 7.1 A Notes: (1) (2) Pulse width limited by safe operating area ) s ( ct Pulsed: pulse duration = 300 µs, duty cycle 1.5% u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O DocID022347 Rev 4 5/15 Electrical characteristics 2.1 STH180N10F3-6 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area GIPG110620141143SA ID (A) 280tok K ᵟ =0.5 100 0.2 is ) ea ar S(on D hi s nt xR i n ma o i y at er d b Op ite Li m 10 0.1 10ms 10 0.05 -1 0.02 1 1ms Tj=175°C Tc=25°C Single pulse 0.1 0.1 1 Single pulse 10 10 -5 10 10 250 bs 200 150 -O 6V 2 4 3 ) s ( ct du so b O tp (s) AM08617v1 5 6 7 o r P 8 250 200 150 100 50 5V 0 V DS(V) Figure 6: Normalized V(BR)DSS vs temperature 0 1 2 3 4 5 6 7 8 9 V GS(V) Figure 7: Static drain-source on-resistance AM08618v1 V (BR)DSS (norm) -1 V DS=2V 300 300 1 10 t e l o 7V 0 10 -2 r P e ID (A) 350 0 10 -3 u d o V GS=10V 50 -4 Figure 5: Transfer characteristics 350 100 ) s ( ct -2 AM08616v1 ID(A) tp t 100µs V DS(V) Figure 4: Output characteristics e t e l Zth=k Rthj-c ᵟ =tp/ t 0.01 AM08626v1 R DS(on) (mΩ) V GS=10V 4.2 ID=1m A 1.10 4.1 4.0 1.05 3.9 1.00 3.8 0.95 0.90 -75 6/15 3.7 3.6 -25 25 75 125 175 T J(°C) DocID022347 Rev 4 0 20 40 60 80 100 120 140 160 180 ID(A) STH180N10F3-6 Electrical characteristics Figure 9: Capacitance variations Figure 8: Gate charge vs gate-source voltage V DD=50V ID=120 A 12 AM08621v1 C (pF) AM08620v1 V GS (V) 20000 10 15000 8 6 10000 Ciss 4 5000 2 Crss 0 0 20 40 80 60 100 120 140 (norm) ID=250µ A 80 100 V DS(V) ) s ( ct u d o 1.9 AM08623v1 r P e 2.1 ID=60 A V GS=10V t e l o 1.1 1.7 1.5 bs 0.9 0.7 0.3 -75 -25 s ( t c 25 u d o Pr 75 1.3 O ) 0.5 s b O 60 40 R DS(on) AM08622v1 1.3 e t e ol 20 Figure 11: Normalized on-resistance vs temperature Figure 10: Normalized gate threshold voltage vs temperature V GS(th) (norm) Coss 0 0 Q g(nC) 125 1.1 0.9 0.7 0.5 -75 175 T J(°C) -25 25 75 125 175 T J(°C) Figure 12: Source-drain diode forward characteristics AM08624v1 V SD (V) 1.0 T J=-55°C 0.9 0.8 T J=25°C 0.7 0.6 0.5 T J=175°C 0.4 0 20 40 60 DocID022347 Rev 4 80 100 120 ISD(A) 7/15 Test circuits 3 STH180N10F3-6 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. VG 2.7 k Ω 2200 μ F ) s ( ct 47 k Ω PW 1 kΩ u d o Figure 15: Test circuit for inductive load switching and diode recovery times ) (s AM01469v 1 r P e Figure 16: Unclamped inductive load test circuit t e l o s b O t c u d o r P e t e l o Figure 17: Unclamped inductive waveform bs Figure 18: Switching time waveform t on V(BR)DSS t d(on) VD O t off tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 8/15 DocID022347 Rev 4 0 10% VDS 90% AM01473v 1 STH180N10F3-6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. H2PAK-6 package information 4.1 Figure 19: H²PAK-6 outline ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 8159693_Rev_F DocID022347 Rev 4 9/15 Package information STH180N10F3-6 Table 8: H²PAK-6 mechanical data mm Dim. Min. Typ. A 4.30 4.80 A1 0.03 0.20 C 1.17 1.37 e 2.34 2.74 e1 4.88 5.28 e2 7.42 7.82 E 0.45 0.60 F 0.50 0.70 H 10.00 H1 7.40 L 14.75 L1 1.27 L2 4.35 L3 6.85 L4 1.5 M 1.90 R 0.20 V 0° ) (s ) s ( ct 10.40 - 7.80 du ro P e t e l o s b O t c u d o r P e t e l o s b O 10/15 Max. DocID022347 Rev 4 15.25 1.40 4.95 7.25 1.75 2.50 0.60 8° STH180N10F3-6 Package information Figure 20: H²PAK-6 recommended footprint ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o footprint_Rev_F Dimensions are in mm. DocID022347 Rev 4 11/15 Package information 4.2 STH180N10F3-6 Packing information Figure 21: Tape outline ) s ( ct u d o r P e t e l o s b O ) (s t c u od Pr Figure 22: Reel outline T REE L DIMENS IONS e t e ol 40 mm min. Acc ess hole bs O At slot location B D C N A Tape slot In core for Full radius At hub Tape start 12/15 G measured DocID022347 Rev 4 STH180N10F3-6 Package information Table 9: Tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity P2 1.9 2.1 Bulk quantity R 50 T 0.25 0.35 W 23.7 24.3 ) (s Min. Max. 330 13.2 26.4 30.4 e t e ol du ) s ( ct 1000 1000 o r P s b O t c u d o r P e t e l o s b O DocID022347 Rev 4 13/15 Revision history 5 STH180N10F3-6 Revision history Table 10: Document revision history Date Revision Changes 10-Oct-2011 1 First version 04-Nov-2011 2  Updated features in cover page 14-Nov-2014 3    Updated: H PAK-6 package mechanical data. Updated: title, features and description. Minor text changes. 26-Nov-2014 4 Updated Table 4: "On/off-state". 2 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 14/15 DocID022347 Rev 4 STH180N10F3-6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. ) s ( ct No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. u d o r P e ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. t e l o Information in this document supersedes and replaces information previously supplied in any prior versions of this document. s b O © 2014 STMicroelectronics – All rights reserved ) (s t c u d o r P e t e l o s b O DocID022347 Rev 4 15/15