STH6N95K5-2

STH6N95K5-2 N-channel 950 V, 1 Ω typ., 6 A MDmesh™ K5 Power MOSFET in a H²PAK-2 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STH6N95K5-2 950 V 1.25 Ω 6A 110 W      Industry’s lowest RDS(on) x area Industry’s best figure of merit (FoM) Ultra low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram D(TAB)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(2, 3) AM15557a.v3 Table 1: Device summary Order code Marking Package Packaging STH6N95K5-2 6N95K5 H²PAK-2 Tape and reel March 2015 DocID027383 Rev 3 This is information on a product in full production. 1/17 www.st.com Contents STH6N95K5-2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package mechanical data ............................................................. 10 4.1 Package mechanical data ............................................................... 11 5 Packing information ...................................................................... 14 6 Revision history ............................................................................ 16 2/17 DocID027383 Rev 3 STH6N95K5-2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Gate-source voltage Value Unit ± 30 V ID Drain current at TC = 25 °C 6 A ID Drain current at TC = 100 °C 3.8 A IDM(1) Drain current (pulsed) 24 A PTOT Total dissipation at TC = 25 °C 110 W IAR(2) Max current during repetitive or single pulse avalanche 3 A EAS(3) Single pulse avalanche energy 90 mJ Peak diode recovery voltage slope 4.5 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C dv/dt (4) dv/dt(5) Tj Operating junction temperature Tstg Storage temperature Notes: (1)Pulse width limited by safe operating area. (2)Pulse width limited by Tjmax. (3)Starting (4)I SD (5)V Tj = 25 °C, ID = IAS, VDD = 50 V. ≤ 6 A, di/dt ≤ 100 A/µs, VDS(peak) ≤ V(BR)DSS. DS ≤ 760 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Thermal resistance junction-case max 1.14 Thermal resistance junction-pcb max 30 Unit °C/W Notes: (1)When mounted on 1 inch² FR-4 board, 2 oz Cu. DocID027383 Rev 3 3/17 Electrical characteristics 2 STH6N95K5-2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. Max. Unit 950 V VGS = 0 V, VDS = 950 V 1 µA VGS = 0 V, VDS = 950 V, Tc = 125 °C 50 µA Gate body leakage current VDS = 0 V, VGS = ± 20 V ± 10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source onresistance VCS = 10 V, ID = 3 A 1 1.25 Ω Min. Typ. Max. Unit - 450 - - 30 - IDSS Zero gate voltage drain current IGSS 3 Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Coss Output capacitance - 1.6 - Co(tr)(1) Equivalent capacitance, timerelated - 45 - Co(er)(2) Equivalent capacitance, energyrelated RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 V, VDS = 100 V, f = 1 MHz pF VGS = 0 V, VDS = 0 to 760 V pF - f = 1 MHz, ID =0 A - VDD = 760 V, ID = 6 A, VGS = 10 V (see Figure 16: "Gate charge test circuit" ) 19 - 7 Ω - - 13 - - 3 - - 7 - nC Notes: (1)Time-related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. (2)Energy-related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS. Table 6: Switching times Symbol td(on) tr td(off) tf 4/17 Parameter Test conditions Turn-on delay time Rise time Turn-off-delay time VDD = 475 V, ID = 3 A, RG = 4.7 Ω, VGS = 10 V Fall time DocID027383 Rev 3 Min. Typ. Max. Unit - 12 - ns - 12 - ns - 33 - ns - 21 - ns STH6N95K5-2 Electrical characteristics Table 7: Source drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 6 A ISDM(1) Source-drain current (pulsed) - 24 A VSD(2) Forward on voltage ISD = 6 A, VGS = 0 - 1.6 V trr Reverse recovery time - 372 ns Qrr Reverse recovery charge - 4 µC IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs VDD = 60 V - 22 A ISD = 6 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C - 522 ns - 5 µC - 20 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 8: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ± 1mA, ID=0 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. DocID027383 Rev 3 5/17 Electrical characteristics 2.1 STH6N95K5-2 Electrical characteristics (curves) Figure 2: Safe operating area ID (A) Figure 3: Thermal impedance GIPG220120151710ALS CG20930 K δ = 0.5 10 n) 100µs D S( o O p lim era ite tion d by in t m his ax a R rea δ = 0.2 δ = 0.1 10-1 1ms δ = 0.05 δ = 0.02 δ = 0.01 0.1 Tj=150°C TC=25°C Single pulse 0.01 0.1 Z Zthth == kk R Rthj-C thj-C δδ == ttp // Ƭ Ƭ p 10ms is 1 1 10 10-5 Figure 4: Output characteristics ID (A) ƬƬ 10 VDS(V) 100 tp SINGLE PULSE -2 10-4 10-3 10-2 10-1 tp(s) Figure 5: Transfer characteristics AM07108v1 AM07109v1 ID (A) VGS=10V 12 8 10 6 8 VDS=15V 7V 6 4 4 2 6V 2 5V 0 0 5 10 15 20 25 Figure 6: Gate charge vs gate-source voltage VGS (V) 12 AM07110v1 VDS 0 VDS(V) 0 VDD=760V ID=6A 8 500 400 6/17 300 0.95 0.93 0.91 0.89 0 0 14 Qg(nC) 10 VGS=10V 0.99 100 8 AM07111v1 1.01 2 6 VGS(V) 1.03 200 4 8 RDS(on) (Ohm) 4 2 6 0.97 6 0 4 Figure 7: Static drain-source on-resistance VDS (V) 700 600 10 2 12 DocID027383 Rev 3 0.87 0.5 1.0 1.5 2.0 2.5 3.0 ID(A) STH6N95K5-2 Electrical characteristics Figure 8: Capacitance variations C (pF) Figure 9: Output capacitance stored energy AM07112v1 AM07113v1 Eoss (µJ) 20 1000 Ciss 100 16 12 Coss 8 Crss 4 VDS(V) 0 10 1 0.1 1 10 100 Figure 10: Normalized gate threshold voltage vs temperature VGS(th) (norm) 1.2 AM07114v1 0 200 400 600 800 VDS(V) Figure 11: Normalized on-resistance vs temperature RDS(on) (norm) AM07115v1 2.5 1.1 ID=100 µA 1.0 2.0 VGS=10V 0.9 1.5 0.8 0.7 1.0 0.6 0.5 0.5 0.4 -75 -25 25 75 125 TJ(°C) Figure 12: Source-drain diode forward characteristics 0 -75 -25 25 75 Tj(°C) Figure 13: Normalized V(BR)DSS vs temperature V(BR)DSS (norm) VSD (V) 125 AM07116v1 1.2 0.95 ID=1 mA 1.1 0.85 1.0 0.75 0.9 0.65 0.55 2.0 0.8 3.0 4.0 5.0 6.0 ISD(A) DocID027383 Rev 3 0.7 -75 -25 25 75 125 Tj(°C) 7/17 Electrical characteristics STH6N95K5-2 Figure 14: Maximum avalanche energy vs starting Tj EAS (mJ) 100 AM07117v1 80 ID=3 A VDD=50 V 60 40 20 0 0 8/17 20 40 60 80 DocID027383 Rev 3 100 120 140 Tj(°C) STH6N95K5-2 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit VDD 47 k Ω 12 V 1 kΩ 100 nF I G = CONST Vi ≤ V GS 100 Ω D.U.T. VG 2.7 k Ω 2200 μ F 47 k Ω 1 kΩ PW AM01469v 1 Figure 17: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 18: Unclamped inductive load test circuit A D G S L=100 µH 3.3 µF B 25 Ω 1000 µF D G RG VDD D.U.T. S AM01470v1 Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform t on V(BR)DSS t d(on) VD t off tr t d(off) tf 90% 90% I DM 10% ID VDD 10% 0 VDD VGS AM01472v 1 0 DocID027383 Rev 3 10% VDS 90% AM01473v 1 9/17 Package mechanical data 4 STH6N95K5-2 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/17 DocID027383 Rev 3 STH6N95K5-2 4.1 Package mechanical data Package mechanical data Figure 21: H²PAK-2 outline 8159712_D DocID027383 Rev 3 11/17 Package mechanical data STH6N95K5-2 Table 9: H²PAK-2 mechanical data mm Dim. Min. 12/17 Typ. Max. A 4.30 4.80 A1 0.03 0.20 C 1.17 1.37 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 H 10.00 10.40 H1 7.40 L 15.30 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.5 1.7 - 7.80 15.80 M 2.6 2.9 R 0.20 0.60 V 0° 8° DocID027383 Rev 3 STH6N95K5-2 Package mechanical data Figure 22: H²PAK-2 recommended footprint 8159712_D DocID027383 Rev 3 13/17 Packing information 5 STH6N95K5-2 Packing information Figure 23: Tape outline 14/17 DocID027383 Rev 3 STH6N95K5-2 Packing information Figure 24: Reel outline T REE L DIMENS IONS 40 mm min. Acc ess hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start Table 10: Tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 DocID027383 Rev 3 Min. Max. 330 13.2 26.4 30.4 15/17 Revision history 6 STH6N95K5-2 Revision history Table 11: Document revision history 16/17 Date Revision Changes 23-Jan-2015 1 First release. 04-Feb-2015 2 Updated Section 2: "Electrical characteristics" 12-Mar-2015 3 Document status changed from preliminary to producion data. DocID027383 Rev 3 STH6N95K5-2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027383 Rev 3 17/17