STHDLS101A
Enhanced AC coupled HDMI level shifter
with configurable HPD output
Features
■
Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■
HDMI level shifting operation up to 2.7 Gbps
per lane
■
Integrated 50 Ω termination resistors for ACcoupled differential inputs
■
Input/output transition minimized differential
signaling (TMDS) enable/disable
■
Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
and eliminate external components such as RC
and choke
■
Fail safe outputs for backdrive protection
■
No re-timing or configuration required
■
Inter-pair output skew < 250 ps, intra-pair
output skew < 10 ps
■
Single power supply of 3.3 V
■
ESD protection: ±6 KV HBM on all I/O pins
■
Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
■
Level shifter and configurable output for HPD
signal from HDMI/DVI connector
■
Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Applications
■
Notebooks, PC motherboards and graphic
cards
Table 1.
Device summary
QFN48
(7 x 7 mm)
Description
The STHDLS101A is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output.
The STHDLS101A supports up to 2.7 Gbps,
which is enough for 12-bits of color depth per
channel, as indicated in HDMI rev 1.3.
The device operates from a single 3.3 V supply
and is available in a 48-pin QFN package.
Order code
Package
Packing
STHDLS101AQTR
QFN48
(7 x 7 x 1 mm)
Tape and reel
June 2009
Doc ID 15756 Rev 1
1/24
www.st.com
24
Contents
STHDLS101A
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
6
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2
Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5
OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6
HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24
Doc ID 15756 Rev 1
STHDLS101A
1
Block diagram
Block diagram
Figure 1.
STHDLS101A block diagram
0V
VCC33
OUT_D4+
50Ω±10%
OUT_D4-
IN _D4+
RX
IN _D4-
OE_N
10mA current
driver
0V
OUT_D3+
50Ω±10%
OUT_D3-
IN _D3+
RX
IN _D3-
10mA current
driver
0V
OUT_D2+
50Ω ±10%
OUT_D2-
IN _D2+
RX
IN _D2-
10mA current
driver
0V
OUT_D1+
50 Ω±10%
OUT_D1-
IN _D1+
RX
IN _D1REXT
10mA current
driver
HPD level shifter
HPD_SOURCE
HPD_SINK
HPD
160K
DDC_EN
SCL_SOURCE
SCL_SINK
SDA_SOURCE
SDA_SINK
Doc ID 15756 Rev 1
3/24
System interface
2
STHDLS101A
System interface
Figure 2.
System inferface
'RAPHICSCHIPSET
'-#( ONTHE
MOTHERBOARD
0#)
%XPRESS
3$6/
($-)
,EVELSHIFTER
34($,3!
($-)OUTPUT
CONNECTOR
!-6
Figure 3.
Cable adapter
($-)$6)
$ONGLEOR
CABLE ADAPTER
34($,3!
$0
!-6
4/24
Doc ID 15756 Rev 1
STHDLS101A
HPD
HDMI/DVI
Transmitter
AC_TMDS
DDC
HPD_SINK
HPD_SOURCE
AC_TMDS
DDC
STHDLS101A
HDMI/DVI Cable
Adaptor
DC TMDS
DDC
HDMI/DVI Connector
DP to HDMI/DVI cable adapter
DP Connector
Figure 4.
System interface
PC chipset
!-6
Doc ID 15756 Rev 1
5/24
Pin configuration
Pin configuration
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STHDLS101A pin configuration
Figure 5.
'.$
3
STHDLS101A
!-6
6/24
Doc ID 15756 Rev 1
STHDLS101A
3.1
Pin configuration
Pin description
Table 2.
Pin description
Pin
number
Name
Type
1
GND
Power
Ground
2
VCC33
Power
3.3 V±10% DC supply
Function
FUNCTION1
Function pins are to enable vendor-specific features or
test modes. For normal operation, these pins are tied to
Vendor-specific GND or VCC33
control or test
For consistent interoperability, GND is the preferred
pins
default connection for these signals. Provides equalizer
6dB lift at high frequencies
4
FUNCTION2
Function pins are to enable vendor-specific features or
test modes
Vendor-specific For normal operation, these pins are tied to GND or
control or test VCC33
pins
For consistent interoperability, GND is the preferred
default connection for these signals. Provides 5 dB
equalizer gain at all frequencies
5
GND
3
6
REXT
Power
Ground
Analog
Connection to external resistor. Resistor value
specified by device manufacturer.
Acceptable connections to this pin are:
– Resistor to GND
– Resistor to 3.3 V
– NC (direct connections to VCC or GND are through a
0 Ω resistor for layout compatibility
Buffer from the 0 V to 5 V input signal. The output
buffer stage is configurable based on the FUNCTION3
pin settings as desribed in the table below:
FUNCTION3
7
8
HPD_SOURCE
SDA_SOURCE
Output
I/O
HPD_SINK
HPD_SOURCE
0
Low
Open-drain,
connected an
external pull up to
the desired
supply
(normally 1 V)
0
High (5 V)
Low (0 V)
1
Low (0 V)
Low (0 V)
1
High (5 V)
High (3 V)
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltagelimiting integrated NMOS pass-gate
Doc ID 15756 Rev 1
7/24
Pin configuration
Table 2.
8/24
STHDLS101A
Pin description (continued)
Pin
number
Name
Type
Function
9
SCL_SOURCE
Input
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltagelimiting integrated NMOS pass-gate
10
ANALOG2
Analog
Analog connection determined by vendor. Acceptable
connections to this pin are:
– Resistor or capacitor to GND
– Resistor or capacitor to 3.3 V
– Short to 3.3 V or to GND
– NC
11
VCC33
Power
3.3 V ±10% DC supply
12
GND
Power
Ground
13
OUT_D4+
Output
HDMI 1.3 compliant TMDS output
OUT_D4+ makes a differential output signal with
OUT_D4-
14
OUT_D4-
Output
HDMI 1.3 compliant TMDS output
OUT_D4- makes a differential output signal with
OUT_D4+
15
VCC33
Power
3.3 V±10% DC supply
16
OUT_D3+
Output
HDMI 1.3 compliant TMDS output
OUT_D3+ makes a differential output signal with
OUT_D3-
17
OUT_D3-
Output
HDMI 1.3 compliant TMDS output
OUT_D3- makes a differential output signal with
OUT_D3+.
18
GND
Power
Ground
19
OUT_D2+
Output
HDMI 1.3 compliant TMDS output
OUT_D2+ makes a differential output signal with
OUT_D2-.
20
OUT_D2-
Output
HDMI 1.3 compliant TMDS output
OUT_D2- makes a differential output signal with
OUT_D2+
21
VCC33
Power
3.3 V±10% DC supply
22
OUT_D1+
Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-
23
OUT_D1-
Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+
24
GND
Power
Ground
Doc ID 15756 Rev 1
STHDLS101A
Pin configuration
Table 2.
Pin
number
Pin description (continued)
Name
Type
Function
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected
25
OE_N
Input
OE_N
IN_D
termination
OUT_D Outputs
1
High-Z
High-Z
0
50 Ω
Active
26
VCC33
Power
3.3 V±10% DC supply
27
GND
Power
Ground
28
SCL_SINK
Output
5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS pass-gate
29
SDA_SINK
I/O
5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS pass-gate
30
HPD_SINK
Input
Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor
31
GND
Power
Ground
Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves)
32
33
34
DDC_EN
VCC33
FUNCTION3
Input
DDC_EN
Pass-gate
0V
Disabled
3.3 V
Enabled
Power
3.3 V±10% DC supply
Input
Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output
sand when H, the HPD_SOURCE is a buffered output
(O V to VCC)
Function pins are to enable vendor-specific features or
test modes
Vendor-specific
For normal operation, these pins are tied to GND or
control or test
VCC33
pins
For consistent interoperability, GND is the preferred
default connection for these signals
35
FUNCTION4
36
GND
Power
Ground
37
GND
Power
Ground
Doc ID 15756 Rev 1
9/24
Pin configuration
Table 2.
10/24
STHDLS101A
Pin description (continued)
Pin
number
Name
Type
Function
38
IN_D1-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+
39
IN_D1+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-
40
VCC33
Power
3.3 V±10% DC supply
41
IN_D2-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+
42
IN_D2+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-
43
GND
Power
Ground
44
IN_D3-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+
45
IN_D3+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-
46
VCC33
Power
3.3 V±10% DC supply
47
IN_D4-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+
48
IN_D4+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-
Doc ID 15756 Rev 1
STHDLS101A
4
Functional description
Functional description
The section describes the basic functionality of the STHDLS101A device.
Power supply
The STHDLS101A is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termina-tion resistors are enabled and any internal bias circuits are turned on.
OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3.
OE_N description
OE_N
Asserted (low level)
or unconnected
Device state
Differential input buffers and
output buffers enabled. Input
impedance = 50Ù
Low-power state.
Differential input buffers and
terminations are disabled.
Differential input buffers are in
high-impedance state.
De-asserted (high level)
Comments
Normal functioning state for IN_D
to OUT_D level shifting function.
Intended for lowest power
condition when:
• No display is plugged in or
• The level shifted data path is
disabled
HPD_SINK input and
OUT_D level shifting outputs are HPD_SOURCE output are not
disabled. OUT_D level shifting
affected by OE_N.
outputs are in a high-impedance
state.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK
Internal bias currents are turned signals and functions are not
off.
affected by OE_N.
Doc ID 15756 Rev 1
11/24
Functional description
Table 4.
STHDLS101A
OE_N function
OE_N
12/24
IN_Dx
OUT_Dx
(TMDS outputs)
Notes
Device disabled.
Low power state.
Internal bias currents are
disabled.
De-asserted
(high level)
High-Z
High-Z
Asserted or
unconnected
(low level)
50 Ω termination
Enabled
Doc ID 15756 Rev 1
Level shifting mode
enabled.
STHDLS101A
5
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Symbol
Parameter
VCC
VI
Value
Unit
Supply voltage to ground potential
-0.5 to +4.0
V
DC input voltage (TMDS and PCIe ports)
-0.5 to +4.0
V
Control pins
-0.5 to +4.0
V
-0.5 to +6
V
SDA_SINK, SCL_SINK, HPD_SINK pins
IO
DC output current
120
mA
PD
Power dissipation
1
W
-65 to +150
°C
300
°C
±6
kV
Storage temperature
TSTG
Lead temperature (10 sec)
TL
Electrostatic discharge
voltage on IOs(1)
VESD
Human body model
1. In accordance with the MIL standard 883 method 3015
Table 6.
Symbol
θJA
Thermal data
Parameter
Junction-ambient thermal coefficient
Doc ID 15756 Rev 1
QFN48
Unit
48
°C/W
13/24
Maximum ratings
STHDLS101A
5.1
Recommended operating conditions
5.1.1
Power supply and temperature range
Table 7.
Power supply and temperature range
Symbol
VCC33
ICC
T
Parameter
Comments
3.3 V power supply
Total current from VCC
3.3 V power supply
Maximum power supply current
Operating temperature range
5.1.2
Differential inputs (IN_D signals)
Table 8.
Differential input characteristics for IN_D signals
Symbol
Tbit
Parameter
VCM-AC-pp
Typ
Max
Unit
3.0
3.3
3.6
V
−
−
120
mA
-40
−
85
o
C
Comments
Min
Typ
Max
Unit
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at
2.5 Gbps = 400 ps. 360 ps =
400 ps – 10%
360
−
−
ps
VRX-DIFFp-p=2*|VRX-D+ - VRXD-|. Applies to IN_D signals.
0.2
−
1.2
V
The level shifter may add a
maximum of 0.02UI jitter
0.8
−
−
Tbit
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
VRX-CM-DC=DC(avg) of
AC peak common mode input voltage
|VRX-D+ + VRX-D-|/2
VCM-AC-pp includes all
frequencies above 30 kHz.
−
−
100
mV
Unit interval
VRX-DIFFp-p Differential input peak to peak voltage
TRX-EYE
Min
Minimum eye width at IN_D input pair
ZRX-DC
DC single-ended input impedance
Applies to IN_D+ as well as
IN_D- pins (50 Ω ± 20%
tolerance)
40
50
60
Ω
VRX-Bias
RX input termination voltage
Intended to limit power-up
stress on chipset’s PCIE
output buffers
0
−
2
V
100
−
−
KΩ
ZRX-HIGH-Z
14/24
Single-ended input resistance for
Differential inputs must be in
IN_Dx when inputs are in high-Z state a high impedance state
Doc ID 15756 Rev 1
STHDLS101A
5.2
Maximum ratings
TMDS outputs (OUT_D signals)
The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.
Table 9.
Symbol
Differential output characteristics for TMDS OUT_D signals
Parameter
Comments
Min
Typ
Max
Unit
AVCC is the DC termination
voltage in the HDMI or DVI
sink. AVCC is nominally 3.3 V
AVCC-10 mV
AVCC
AVCC+10 m
V
V
AVCC600 mV
AVCC500 mV
AVCC400 mV
V
400 mV
500 mV
600 mV
V
−
−
10
µA
VH
Single-ended high
level output voltage
VL
Single-ended low level The open-drain output pulls
output voltage
down form AVCC
VSWING
Single-ended output
swing voltage
Swing down from TMDS
termination voltage
(3.3 V ±10%)
IOFF
Single-ended current
in high-Z state
Measured with TMDS outputs
pulled up to AVCC max (3.6 V)
through 50 Ω resistors
TR
Rise time
Maximum rise/fall time at
2.7 Gbps = 148ps. 125ps =
148 – 15%
125 ps
−
0.4 Tbit
ps
TF
Fall time
Maximum rise/fall time at
2.7 Gbps = 148 ps.
125ps = 148 – 15%
125 ps
−
0.4 Tbit
ps
TSKEW- Intra-pair differential
skew
INTRA
This differential skew budget
is in addition to the skew
presented between D+ and Dpaired input pins.
−
−
10
ps
TSKEW- Inter-pair lane to lane
output skew
INTER
This lane to lane skew budget
is in addition to the skew
between differential input
pairs.
−
−
250
ps
Jitter added to TMDS
signals
Jitter budget for TMDS
signals as they pass through
the level shifter.
7.4 ps = 0.02 Tbit at 2.7 Gbps
−
−
7.4
ps
TJIT
Doc ID 15756 Rev 1
15/24
Maximum ratings
STHDLS101A
5.3
HPD input and output characteristics
Table 10.
HPD_SINK input and HPS_SOURCE output
Symbol
Parameter
Comment
Min
Typ
Max
Unit
Low speed input changes
state on cable plug/unplug
2
5.0
5.3
V
0
−
0.8
V
−
−
50
µA
VIH-HPD_SINK
HPD_SINK input high level
VIL-HPD_SINK
HPD_SINK input low level
IIN-HPD_SINK
HPD_SINK input leakage current
Measured with HPD_SINK
at VIH-HPD max and VILHPD min
VOL-
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V ±10%
2.5
−
VCC
V
HPD_SOURCE output high level
when FUNCTION3 = L
VCC = 3.3 V ±10%
IOL = 1 mA
0
−
0.2
V
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V ±10%
0
−
0.2
V
HPD_SINK to HPD_SOURCE
propagation delay
Time from HPD_SINK
changing state to
HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall
time
CL=10 pF
−
−
200
ns
1
−
20
ns
HPD_SOURCE
VOHHPD_SOURCE
(INV)
VOLHPD_SOURCE
THPD
TRF-HPD
HPD_SOURCE rise/fall time
Time required to transition
from VOH-HPD_SOURCE to
VOL-HPD_SOURCE or from
VOL-HPD_SOURCE to VOHHPD_SOURCE
CL=10 pF
16/24
Doc ID 15756 Rev 1
STHDLS101A
Maximum ratings
5.4
DDC input and output chatacteristics
Table 11.
SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Symb
ol
Comment
Min
Typ
Max
Unit
Voltage on the DDC pins on
connector end
0
−
5.5
V
ILKG
VCC = 3.3 V
VI =0.1VDD to 0.9 VDD to
isolated DDC inputs
Input leakage current on SDA_SINK, SCL_SINK
VDD = external pull-up
pins
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
-10
−
10
µA
IOFF
Power-down leakage current on SDA_SINK,
SCL_SINK pins
VCC = 0.0 V
VI = 0.1 VDD to 0.9 VDD to
DDC sink inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
SDA_SOURCE,
SCL_SOURCE = 0.0 V
-10
−
10
µA
CI/O
Input/output capacitance
(switch off)
VI(pp)=1 V, 100 KHz
VCC=3.3 V, T=25C
−
5
−
pF
CI/O
Input/output capacitance
(switch on)
VI(pp)=1 V, 100KHz
VCC = 3.3 V, T= 25 ° C
−
−
10
pF
RON
Switch resistance
IO=3 mA, VO = 0.4 V
VCC = 3.3 V
−
27
40
Ω
TPD
Time from DDC_SINK
changing state to
DDC_SOURCE changing
state while the pass gate is
DDC_SINK to DDC_SOURCE propagation delay enabled.
CL=10 pF
RPU=1.5 K (min), 2.0 K
(max)
−
8
15
ns
TSX
Switch time from DDC_EN to the valid state on
DDC_SOURCE
−
8
15
ns
VI
Parameter
Input voltage on SDA_SINK, SCL_SINK pins
CL = 10 pF
RPU = 1.5 K (min), 2.0 K
(max)
Doc ID 15756 Rev 1
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Maximum ratings
STHDLS101A
5.5
OE_ input characteristics
Table 12.
OE_N input characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VIH-OE_N Input high level
2
−
VCC33
V
VIL-OE_N
Input low level
0
−
0.8
V
IIN-OE_N
Input leakage current
−
−
200
µA
5.6
HPD input resistor
Table 13.
HDP input resistor
Symbol
RHPD
Parameter
HPD_SINK input pull-down resistor
5.7
ESD performance
Table 14.
ESD performance
Comment
Measured with OE_N at
VIH-OE_N max and VILOE_N min
Comment
Guarantees HPD_SINK is
LOW when no display is
plugged in
Min
Typ
Max
Unit
130 K
160 K
190 K
Ω
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
ESD
MIL STD 883 method 3015 (all pins)
Human Body Model (HBM)
-6
−
+6
kV
18/24
Doc ID 15756 Rev 1
STHDLS101A
Application information
6
Application information
6.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is
recommended to always apply VCC before applying any signals to the input/output
or control pins.
6.2
Supply bypassing
Bypass each of the VCC pins with 0.1 µF and 1nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device
as possible.
6.3
Differential traces
The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on these transmission lines between
the connectors and the device.
(a) Maintain 100 Ω differential transmission line impedance into and out of the device.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential outputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STHDLS101A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
Doc ID 15756 Rev 1
19/24
Package mechanical data
7
STHDLS101A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 6.
20/24
Package outline for QFN48 (7 x 7 x 1 mm) - 0.5 mm pitch
Doc ID 15756 Rev 1
STHDLS101A
Package mechanical data
Table 15.
Package mechanical data for QFN48 (7 x 7 x 1 mm) - 0.5 mm pitch
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.80
0.90
1.00
0.80
0.85
1.00
A1
−
0.02
0.05
−
0.01
0.05
A2
−
0.65
1.00
−
0.65
−
A3
−
0.25
−
−
0.20
−
b
0.18
0.23
0.30
0.18
0.23
0.30
D
6.85
7.00
7.15
6.90
7.00
7.10
D2
2.25
4.70
5.25
E
6.85
7.00
7.15
E2
2.25
4.70
5.25
e
0.45
0.50
0.55
0.45
0.50
0.55
L
0.30
0.40
0.50
0.30
0.40
0.50
ddd
−
−
0.08
−
−
0.08
Figure 7.
SEE EXPOSED PAD VARIATIONS
6.90
7.00
7.10
SEE EXPOSED PAD VARIATIONS
Tape information for QFN48 (7 x 7 x 1 mm) - 0.5 mm pitch
Doc ID 15756 Rev 1
21/24
Package mechanical data
Figure 8.
STHDLS101A
Reel information for QFN48 (7 x 7 x 1 mm) - 0.5 mm pitch
0084694_J
Table 16.
22/24
Reel mechanical data (dimensions in mm)
A
C
N
T
330.2
13 ±0.25
100
16.4
Doc ID 15756 Rev 1
STHDLS101A
8
Revision history
Revision history
Table 17.
Document revision history
Date
Revision
22-Jun-2009
1
Changes
Initial release.
Doc ID 15756 Rev 1
23/24
STHDLS101A
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