STHDLS101T
AC coupled HDMI level shifter
with configurable HPD output
Features
■
Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■
HDMI level shifting operation up to 2.7 Gbps
per lane
■
Integrated 50-Ω termination resistors for ACcoupled differential inputs
■
Input/output transition minimized differential
signaling (TMDS) enable/disable
■
Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
■
Fail safe outputs for backdrive protection
■
No re-timing or configuration required
■
Inter-pair output skew < 250 ps
■
Intra-pair output skew < 10 ps
■
Single power supply of 3.3 V
■
ESD protection: ±6 KV HBM on all I/O pins
■
Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
■
Level shifter and configurable output for HPD
signal from HDMI/DVI connector
■
Integrated pull-down resistor on HPD_SINK
and OE_N inputs
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Notebooks
■
PC motherboards and graphic cards
■
Dongles/cable adapters
Table 1.
QFN-48
(7 x 7 mm)
ODescription
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The STHDLS101T is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output.
The STHDLS101T supports up to 2.7 Gbps,
which is enough for 12-bits of color depth per
channel, as indicated in HDMI rev 1.3. The device
operates from a single 3.3 V supply and is
available in a 48-pin QFN package.
Device summary
Order code
Package
Packaging
STHDLS101TQTR
QFN-48
Tape and reel
December 2008
Rev 3
1/26
www.st.com
26
Contents
STHDLS101T
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
System interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
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Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
6
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Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1
Power supply and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2
Differential inputs (IN_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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5.2
TMDS outputs (OUT_D signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
HPD input and output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
DDC input and output chatacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5
OE_ input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6
HPD input resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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6.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
O
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/26
STHDLS101T
Contents
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Block diagram
1
STHDLS101T
Block diagram
Figure 1.
STHDLS101T block diagram
0V
VCC33
OUT_D4+
50Ω±10%
OUT_D4-
IN _D4+
RX
IN _D4-
OE_N
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10mA current
driver
0V
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50Ω±10%
OUT_D3+
OUT_D3-
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IN _D3+
RX
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IN _D3-
0V
)-
50Ω ±10%
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10mA current
driver
OUT_D2+
OUT_D2-
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IN _D2+
RX
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IN _D2-
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10mA current
driver
0V
OUT_D1+
50 Ω±10%
OUT_D1-
IN _D1+
RX
IN _D1REXT
10mA current
driver
HPD level shifter
HPD_SOURCE
DDC_EN
4/26
HPD_SINK
HPD
160K
SCL_SOURCE
SCL_SINK
SDA_SOURCE
SDA_SINK
STHDLS101T
2
System interface
System interface
Figure 2.
System inferface
Graphics chipset
(GMCH) on the
motherboard
PCI-Express
SDVO
HDMI
Level shifter
HDMI output
connector
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STHDLS101T
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Figure 3.
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Cable adapter
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($-)$6)
$ONGLEOR
CABLE ADAPTER
34($,34
$0
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5/26
System interface
STHDLS101T
DP to HDMI/DVI cable adapter
AC_TMDS
DDC
DP Connector
HPD
HDMI/DVI
Transmitter
HPD_SINK
HDMI/DVI Connector
Figure 4.
HPD_SOURCE
DC TMDS
STHDLS101T
HDMI/DVI Cable
Adaptor
AC_TMDS
DDC
DDC
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PC chipset
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STHDLS101T
Pin configuration
IN_D1IN_D1+
GND
VCC33
OE_N
27
26
25
30
SDA_SINK
HPD_SINK
31
SCL_SINK
GND
32
29
DDC_EN
33
28
FUNCTION3
VCC33
34
FUNCTION4
35
24
GND
37
23
OUT_D1-
38
22
OUT_D1+
39
VCC33
IN_D2+
QFN-48
19
42
GND
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43
IN_D3IN_D3+
44
46
GND
OUT_D3-
8
9
10
11
12
SDA_SOURCE
SCL_SOURCE
ANALOG2
VCC33
GND
OUT_D4+
7
13
HPD_SOURCE
OUT_D4-
6
VCC33
14
REXT
15
4
3
FUNCTION1
OUT_D2+
OUT_D3+
5
2
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VCC33
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48
OUT_D2-
16
GND
47
IN_D4+
VCC33
17
FUNCTION2
IN_D4-
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VCC33
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41
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40
IN_D2-
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GND
GND
36
STHDLS101T pin configuration
1
Figure 5.
GND
3
Pin configuration
CS000118
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Pin configuration
3.1
STHDLS101T
Pin description
Table 2.
Pin description
Pin
number
Name
Type
1
GND
Power
Ground
2
VCC33
Power
3.3V±10% DC supply
FUNCTION1
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
For normal operation, these pins are tied to GND or
control or test
VCC33.
pins
For consistent interoperability, GND is the preferred
default connection for these signals
4
FUNCTION2
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
For normal operation, these pins are tied to GND or
control or test
VCC33.
pins
For consistent interoperability, GND is the preferred
default connection for these signals
5
GND
3
6
7
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Power
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REXT
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HPD_SOURCE
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Analog
Output
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Ground
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Connection to external resistor. Resistor value
specified by device manufacturer.
Acceptable connections to this pin are:
- Resistor to GND
- Resistor to 3.3V;
- NC (direct connections to VCC or GND are through a
0-Ù resistor for layout compatibility
Buffer from the 0 V to 5 V input signal. The output
buffer stage is configurable based on the FUNCTION3
pin settings as desribed in the table below:
FUNCTION3
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Function
HPD_SINK
HPD_SOURCE
0
Low
Open-drain,
connected an
external pull up to
the desired
supply
(normally 1 V)
0
High (5 V)
Low (0 V)
1
Low (0 V)
Low (0 V)
1
High (5 V)
High (3 V)
8
SDA_SOURCE
I/O
3.3 V DDC data I/O. Pulled-up by external termination
to 3.3 V. Connected to SDA_SINK through voltagelimiting integrated NMOS pass-gate
9
SCL_SOURCE
Input
3.3 V DDC clock I/O. Pulled-up by external termination
to 3.3 V. Connected to SCL_SINK through voltagelimiting integrated NMOS pass-gate
STHDLS101T
Pin configuration
Table 2.
Pin description (continued)
Pin
number
Type
Function
10
ANALOG2
Analog
Analog connection determined by vendor.
Acceptable connections to this pin are:
- Resistor or capacitor to GND
- Resistor or capacitor to 3.3 V
- Short to 3.3 V or to GND
- NC
11
VCC33
Power
3.3 V ±10% DC supply
12
GND
Power
Ground
13
OUT_D4+
Output
HDMI 1.3 compliant TMDS output.
OUT_D4+ makes a differential output signal with
OUT_D4-.
14
OUT_D4-
Output
HDMI 1.3 compliant TMDS output.
OUT_D4- makes a differential output signal with
OUT_D4+.
15
VCC33
Power
3.3 V±10% DC supply
16
OUT_D3+
Output
HDMI 1.3 compliant TMDS output.
OUT_D3+ makes a differential output signal with
OUT_D3-.
17
OUT_D3-
Output
18
GND
19
OUT_D2+
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HDMI 1.3 compliant TMDS output.
OUT_D3- makes a differential output signal with
OUT_D3+.
Power
Ground
Output
HDMI 1.3 compliant TMDS output.
OUT_D2+ makes a differential output signal with
OUT_D2-.
OUT_D2-
Output
HDMI 1.3 compliant TMDS output.
OUT_D2- makes a differential output signal with
OUT_D2+.
21
VCC33
Power
3.3 V±10% DC supply
22
OUT_D1+
Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
23
OUT_D1-
Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
24
GND
Power
Ground
20
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Name
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Pr
Enable for level shifter path. 3.3 V tolerant low-voltage
single-ended input. Internal pull-down enables chip
when unconnected.
25
26
OE_N
VCC33
Input
Power
OE_N
IN_D
termination
OUT_D Outputs
1
High-Z
High-Z
0
50 Ω
Active
3.3 V±10% DC supply
9/26
Pin configuration
STHDLS101T
Table 2.
Pin description (continued)
Pin
number
Name
Type
27
GND
Power
Ground
28
SCL_SINK
Output
5 V DDC Clock I/O. Pulled-up by external termination
to 5 V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS pass-gate
29
SDA_SINK
I/O
5V DDC Data I/O. Pulled-up by external termination to
5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS pass-gate
Function
30
HPD_SINK
Input
Low-frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage high
indicates “plugged” state; voltage low indicates
“unplugged” state. HPD_SINK is pulled down by an
integrated 160KΩ pull-down resistor.
31
GND
Power
Ground
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Enables bias voltage to the DDC pass-gate level shifter
gates. (May be implemented as a bias voltage
connection to the DDC pass-gate themselves).
32
DDC_EN
Input
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DDC_EN
bs
0V
-O
3.3 V
33
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VCC33
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Pr
FUNCTION4
Disabled
Enabled
Power
3.3V±10% DC supply
Input
Used for polarity control of the HPD_SOURCE output.
When L, the HPD_SOURCE is an open-drain output
sand when H, the HPD_SOURCE is a buffered output
(O V to VCC)
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FUNCTION3
Pass-gate
Function pins are to enable vendor-specific features or
test modes.
Vendor-specific
For normal operation, these pins are tied to GND or
control or test
VCC33.
pins
For consistent interoperability, GND is the preferred
default connection for these signals
36
GND
Power
Ground
37
GND
Power
Ground
38
IN_D1-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1- makes a differential pair with IN_D1+.
39
IN_D1+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1-.
40
VCC33
Power
3.3 V±10% DC supply
41
IN_D2-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2- makes a differential pair with IN_D2+.
42
IN_D2+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2-.
STHDLS101T
Pin configuration
Table 2.
Pin description (continued)
Pin
number
Name
Type
43
GND
Power
Ground
44
IN_D3-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D3- makes a differential pair with IN_D3+.
45
IN_D3+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3-.
46
VCC33
Power
3.3 V±10% DC supply
47
IN_D4-
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D4- makes a differential pair with IN_D4+.
48
IN_D4+
Input
Low-swing differential input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4-.
Function
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Functional description
4
STHDLS101T
Functional description
The section describes the basic functionality of the STHDLS101T device.
Power supply
The STHDLS101T is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
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Reset
This device acts as a level shifter, reset is not required.
OE_N function
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When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termina-tion resistors are enabled and any internal bias circuits are turned on.
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OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
)
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The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3.
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OE_N description
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OE_N
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Asserted (low level)
or unconnected
Differential input buffers and
output buffers enabled. Input
impedance = 50Ù
Low-power state.
s
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Differential input buffers and
terminations are disabled.
Differential input buffers are in
high-impedance state.
De-asserted (high level)
12/26
Device state
Comments
Normal functioning state for IN_D
to OUT_D level shifting function.
Intended for lowest power
condition when:
• No display is plugged in or
• The level shifted data path is
disabled
HPD_SINK input and
OUT_D level shifting outputs are HPD_SOURCE output are not
disabled. OUT_D level shifting
affected by OE_N.
outputs are in a high-impedance
state.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK
Internal bias currents are turned signals and functions are not
off.
affected by OE_N.
STHDLS101T
Functional description
Table 4.
OE_N function
OE_N
IN_Dx
OUT_Dx
(TMDS outputs)
Notes
Device disabled.
Low power state.
Internal bias currents are
disabled.
De-asserted
(high level)
High-Z
High-Z
Asserted or
unconnected
(low level)
50 Ω termination
Enabled
Level shifting mode
enabled.
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Maximum ratings
5
STHDLS101T
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Absolute maximum ratings
Symbol
Parameter
VCC
VI
Value
Supply voltage to ground potential
-0.5 to +4.0
DC input voltage (TMDS and PCIe ports)
-0.5 to +4.0
Control pins
-0.5 to +4.0
IO
DC output current
PD
Power dissipation
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Storage temperature
TL
Lead temperature (10 sec)
Electrostatic discharge
voltage on IOs(1)
VESD
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Human body model
Pr
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SDA_SINK, SCL_SINK, HPD_SINK pins
TSTG
Unit
V
V
V
-0.5 to +6
V
120
mA
1
W
-65 to +150
°C
300
°C
±6
kV
1. In accordance with the MIL standard 883 method 3015
Table 6.
Symbol
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Thermal data
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14/26
Parameter
Junction-ambient thermal coefficient
QFN-48
Unit
48
°C/W
STHDLS101T
Maximum ratings
5.1
Recommended operating conditions
5.1.1
Power supply and temperature range
Table 7.
Power supply and temperature range
Symbol
VCC33
ICC
T
Parameter
Comments
3.3 V power supply
Operating temperature range
Differential inputs (IN_D signals)
Table 8.
Differential input characteristics for IN_D signals
Parameter
Comments
Tbit is determined by the
display mode. Nominal bit
rate ranges from 250 Mbps
to 2.5 Gbps per lane.
Nominal Tbit at
2.5 Gbps = 400 ps. 360 ps =
400 ps – 10%
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Unit interval
)-
VRX-DIFFp-p Differential input peak to peak voltage
TRX-EYE
VCM-AC-pp
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Minimum eye width at IN_D input pair
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Unit
3.0
3.3
3.6
V
100
mA
s
b
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The level shifter may add a
maximum of 0.02UI jitter
u
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Min
Typ
0.175
1.2
0.8
DC single-ended input impedance
Applies to IN_D+ as well as
IN_D- pins (50 Ω ± 20%
tolerance)
40
VRX-Bias
RX input termination voltage
Intended to limit power-up
stress on chipset’s PCIE
output buffers
0
100
Unit
ps
V
Tbit
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Single-ended input resistance for
Differential inputs must be in
IN_Dx when inputs are in high-Z state a high impedance state
Max
360
ZRX-DC
ZRX-HIGH-Z
C
)
s
(
ct
Pr
VRX-DIFFp-p=2*|VRX-D+ - VRXD-|. Applies to IN_D signals.
o
85
VCM-AC-pp=|VRX-D+ +
VRX-D-|/2 – VRX-CM-DC.
VRX-CM-DC=DC(avg) of
AC peak common mode input voltage
|VRX-D+ + VRX-D-|/2
VCM-AC-pp includes all
frequencies above 30 kHz.
t
e
l
o
bs
Max
-40
5.1.2
Tbit
Typ
Total current from VCC
3.3 V power supply
Maximum power supply current
Symbol
Min
50
100
mV
60
Ω
2
V
KΩ
15/26
Maximum ratings
5.2
STHDLS101T
TMDS outputs (OUT_D signals)
The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The
HDMI 1.3 specification is assumed to be the correct reference in instances where this
document conflicts with the HDMI 1.3 specification.
Table 9.
Symbol
Differential output characteristics for TMDS OUT_D signals
Parameter
Comments
Min
Typ
Max
Unit
AVCC is the DC termination
voltage in the HDMI or DVI
sink. AVCC is nominally 3.3 V
AVCC-10 mV
AVCC
AVCC+10 m
V
V
AVCC600 mV
AVCC500 mV
AVCC400 mV
400 mV
500 mV
t
c
u
(s)
600 mV
V
10
µA
125 ps
0.4 Tbit
ps
125 ps
0.4 Tbit
ps
This differential skew budget
is in addition to the skew
presented between D+ and Dpaired input pins.
10
ps
This lane to lane skew budget
is in addition to the skew
between differential input
pairs.
250
ps
Jitter budget for TMDS
signals as they pass through
the level shifter.
7.4 ps = 0.02 Tbit at 2.7 Gbps
7.4
ps
VH
Single-ended high
level output voltage
VL
Single-ended low level The open-drain output pulls
output voltage
down form AVCC
VSWING
IOFF
TR
TF
Single-ended output
swing voltage
Swing down from TMDS
termination voltage
(3.3 V ±10%)
Single-ended current
in high-Z state
Measured with TMDS outputs
pulled up to AVCC max (3.6 V)
through 50 Ω resistors
Rise time
Maximum rise/fall time at
2.7 Gbps = 148ps. 125ps =
148 – 15%
Fall time
Maximum rise/fall time at
2.7 Gbps = 148 ps.
125ps = 148 – 15%
)-
TSKEW- Intra-pair differential
skew
INTRA
u
d
o
Pr
TSKEW- Inter-pair lane to lane
output skew
INTER
s
b
O
e
t
e
ol
TJIT
16/26
Jitter added to TMDS
signals
t
e
l
o
s
b
O
s
(
t
c
P
e
d
o
r
V
STHDLS101T
Maximum ratings
5.3
HPD input and output characteristics
Table 10.
HPD_SINK input and HPS_SOURCE output
Symbol
Parameter
Comment
Min
Typ
Max
Unit
Low speed input changes
state on cable plug/unplug
2
5.0
5.3
V
0.8
V
50
µA
VIH-HPD_SINK
HPD_SINK input high level
VIL-HPD_SINK
HPD_SINK input low level
IIN-HPD_SINK
HPD_SINK input leakage current
Measured with HPD_SINK
at VIH-HPD max and VILHPD min
HPD_SOURCE output high level
when FUNCTION3 = L
VCC = 3.3 V ±10%
Based on external pull-up
resistor;
output is open drain.
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V ±10%
HPD_SOURCE output high level
when FUNCTION3 = L
VCC = 3.3 V ±10%
IOL = 1 mA
HPD_SOURCE output low level
when FUNCTION3 = H
VCC = 3.3 V ±10%
VOHHPD_SOURCE
0
(INV)
VOLHPD_SOURCE
VOHHPD_SOURCE
(INV)
VOLHPD_SOURCE
THPD
u
d
o
e
t
e
l
TRF-HPD
b
O
so
Pr
HPD_SOURCE rise/fall time
o
s
b
VCC
V
0
0.2
V
0
0.2
V
200
ns
20
ns
Time from HPD_SINK
changing state to
HPD_SOURCE changing
state. Includes
HPD_SOURCE rise/fall
time
CL=10 pF
Time required to transition
from VOH-HPD_SOURCE to
VOL-HPD_SOURCE or from
VOL-HPD_SOURCE to VOH-
u
d
o
Pr
2.5
O
)
s
(
t
c
HPD_SINK to HPD_SOURCE
propagation delay
e
t
e
l
)
s
(
ct
1
HPD_SOURCE
CL=10 pF
17/26
Maximum ratings
STHDLS101T
5.4
DDC input and output chatacteristics
Table 11.
SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics
Symb
ol
Parameter
Input voltage on SDA_SINK, SCL_SINK pins
VI
Comment
Min
Voltage on the DDC pins on
connector end
ILKG
VCC = 3.3 V
VI =0.1VDD to 0.9 VDD to
isolated DDC inputs
Input leakage current on SDA_SINK, SCL_SINK
VDD = external pull-up
pins
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
IOFF
VCC = 0.0 V
VI = 0.1 VDD to 0.9 VDD to
DDC sink inputs
VDD = external pull-up
resistor voltage on
SDA_SINK and SCL_SINK
inputs (maximum of 5.5 V)
SDA_SOURCE,
SCL_SOURCE = 0.0 V
Power-down leakage current on SDA_SINK,
SCL_SINK pins
t
e
l
o
s
b
O
VI(pp)=1 V, 100 KHz
VCC=3.3 V, T=25C
Input/output capacitance
(switch off)
CI/O
Input/output capacitance
(switch on)
RON
Switch resistance
TPD
Time from DDC_SINK
changing state to
DDC_SOURCE changing
state while the pass gate is
DDC_SINK to DDC_SOURCE propagation delay enabled.
CL=10 pF
RPU=1.5 K (min), 2.0 K
(max)
18/26
u
d
o
r
P
e
Switch time from DDC_EN to the valid state on
DDC_SOURCE
Unit
0
5.5
V
-10
10
µA
10
µA
)
s
(
ct
u
d
o
-10
5
VI(pp)=1 V, 100KHz
VCC = 3.3 V, T= 25 ° C
IO=3 mA, VO = 0.4 V
VCC = 3.3 V
t
e
l
o
s
b
O
TSX
s
(
t
c
Max
r
P
e
CI/O
)-
Typ
CL = 10 pF
RPU = 1.5 K (min), 2.0 K
(max)
pF
10
pF
27
40
Ω
8
15
ns
8
15
ns
STHDLS101T
Maximum ratings
5.5
OE_ input characteristics
Table 12.
OE_N input characteristics
Symbol
Parameter
Comment
Min
Typ
Max
Unit
VIH-OE_N Input high level
2
VCC33
V
VIL-OE_N
Input low level
0
0.8
V
IIN-OE_N
Input leakage current
200
µA
Measured with OE_N at
VIH-OE_N max and VILOE_N mix
5.6
HPD input resistor
Table 13.
HDP input resistor
Symbol
RHPD
)
s
(
ct
Parameter
5.7
ESD performance
Table 14.
ESD performance
t
c
u
Parameter
ESD
MIL STD 883 method 3015 (all pins)
r
P
e
t
e
l
o
Guarantees HPD_SINK is
LOW when no display is
plugged in
)
(s
Symbol
od
r
P
e
Comment
HPD_SINK input pull-down resistor
u
d
o
Min
Typ
Max
Unit
130 K
160 K
190 K
Ω
s
b
O
Test condition
Min
Human Body Model (HBM)
-6
Typ
Max
Unit
+6
kV
t
e
l
o
s
b
O
19/26
Application information
STHDLS101T
6
Application information
6.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is
recommended to always apply VCC before applying any signals to the input/output
or control pins.
6.2
Supply bypassing
Bypass each of the VCC pins with 0.1 µF and 1nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device
as possible.
)
s
(
ct
6.3
u
d
o
Differential traces
r
P
e
The high-speed inputs and TMDS outputs are the most critical parts for the device. There
are several considerations to minimize discontinuities on these transmission lines between
the connectors and the device.
t
e
l
o
(a) Maintain 100 Ω differential transmission line impedance into and out of the device.
s
b
O
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
)
(s
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
t
c
u
(d) Layout of the TMDS differential outputs should be with the shortest stubs from the
connectors.
d
o
r
Output trace characteristics affect the performance of the STHDLS101T. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
P
e
t
e
l
o
s
b
O
20/26
STHDLS101T
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
21/26
Package mechanical data
Figure 6.
STHDLS101T
QFN-48 (7 x 7 mm) package outline
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
22/26
s
b
O
STHDLS101T
Package mechanical data
Table 15.
QFN-48 (7 x 7 mm) package mechanical data
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.80
0.90
1.00
0.80
0.85
1.00
A1
0.02
0.05
0.01
0.05
A2
0.65
1.00
0.65
A3
0.25
0.20
b
0.18
0.23
0.30
0.18
0.23
0.30
D
6.85
7.00
7.15
6.90
7.00
7.10
D2
2.25
4.70
5.25
E
6.85
7.00
7.15
E2
2.25
4.70
5.25
e
0.45
0.50
0.55
0.45
L
0.30
0.40
0.50
0.30
0.08
e
t
e
ol
ddd
Figure 7.
6.90
7.00
u
d
o
7.10
SEE EXPOSED PAD VARIATIONS
QFN-48 tape and reel information
)
(s
)
s
(
ct
SEE EXPOSED PAD VARIATIONS
Pr
0.50
0.40
0.55
0.50
0.08
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
23/26
Package mechanical data
Figure 8.
STHDLS101T
Reel information
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
ct
Table 16.
l
o
s
b
O
24/26
u
d
o
0084694_J
Reel mechanical data (dimensions in mm)
Pr
A
ete
)
(s
s
b
O
330.2
C
N
T
13 ±0.25
100
16.4
STHDLS101T
8
Revision history
Revision history
Table 17.
Document revision history
Date
Revision
30-Jun-2008
1
Initial release.
24-Sep-2008
2
Document status promoted from preliminary data to datasheet.
Modified: features section, Table 2: Pin description on page 8 and
Section 4: Functional description.
3
Updated: Features section andChapter 5: Maximum ratings
Added: Figure 3: Cable adapter on page 5 , Figure 4: DP to
HDMI/DVI cable adapter on page 6, Figure 8: Reel information on
page 24 and Table 16: Reel mechanical data (dimensions in mm) on
page 24
01-Dec-2008
Changes
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
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o
s
b
O
25/26
STHDLS101T
)
s
(
ct
Please Read Carefully:
u
d
o
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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r
P
e
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)
(s
s
b
O
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c
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s
b
O
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26/26