STHDMI002A
Wide bandwidth, 2 to 1 HDMI switch with single enable
Features
■
Compatible with HDMI v1.2, DVI v1.0 digital
interfaces
■
165MHz speed operation supports all video
formats up to 1080p and SXGA (1280 x 1024
at 75Hz)
■
Data rate per channel for UXGA: 1.65Gbps
■
Low RON: 5.5 Ω(typ)
■
VCC operating range: 3.135V to 3.465V
■
Low current consumption: 20µA
■
ESD human body model HBM Voltage:
– ±2KV for all I/Os
■
Channel ON capacitance: 6pF (typ)
■
Switching speed: 9ns
■
Near-zero propagation delay: 250ps
■
Low crosstalk: -32dB at 825MHz
■
Bit-to-bit skew: 200ps
■
Very low ground bounce in flow through mode
■
Data and control inputs provide an undershoot
clamp diode
■
Wide bandwidth minimizes skew and jitter
■
Hot insertion capable
■
Isolated Digital Display Control (DDC) bus for
unused ports
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5V tolerance to all DDC and HPD_SINK inputs
■
Supports bi-directional operation
■
Available in the TQFP48 package
■
–40°C to 85°C operating temperature range
Applications
■
Advanced TVs
■
Front projectors
■
LCD TVs
■
PDPs
■
LCD monitors
■
Notebook PCs
■
STB and DVD players
October 2006
The STHDMI002A is a differential Single Pole
Double Throw (SPDT) 2 to 1, low Ron,
bi-directional HDMI switch designed for advanced
TV applications supporting HDMI/DVI which
demand high definition superior image quality.
The differential signal from the 2 ports of HDMI is
multiplexed through the switch to form a single
output HDMI channel going to the HDMI receiver
while the unselected output goes to the high-Z
state.
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Description
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TQFP48
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It is designed for very low cross-talk, low bit-to-bit
skew, high channel-to-channel noise isolation and
low I/O capacitance. The switch offers very little or
practically no attenuation of the high-speed
signals at the outputs, thus preserving the signal
integrity to pass stringent requirements.
The STHDMI002A also includes the DDC as well
as the HPD line switching. The pin layout is
optimized for easy PCB routing to the HDMI
connector and HDMI receivers.
The maximum DVI/HDMI data rate of 1.65Gbps
provides the resolution required by the advanced
HDTV and PC graphics.
Advantages
STHDMI002A provides the ability to switch a
single source output to various display devices or
switch video display devices between multiple
sources. It reduces the overall BOM costs by
eliminating the need for more costly multi inputoutput controllers.
Rev 1
1/26
www.st.com
26
STHDMI002A
Contents
Contents
1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
Function table
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Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3
Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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6.1
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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9
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Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STHDMI002A
Contents
9.2
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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3/26
STHDMI002A
Functional diagram
1
Functional diagram
Figure 1.
Functional diagram
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4/26
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STHDMI002A
2
Functional description
Functional description
The STHDMI002A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standards like TMDS. The device multiplexes
differential outputs from a video source to one of the two corresponding outputs to a common
display. The low on-resistance and low I/O capacitance of STHDMI002A result in a very small
propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS
channels and 1 differential clock channel. Additionally it integrates the switches for DDC and
HPD lines switching.
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The I²C interface of the selected input port is linked to the I²C interface of the output port, and
the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused
ports, the I²C interfaces are isolated, and the HPD pins are also isolated.
2.1
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HPD pins
The input of the Y_HPD is 5V tolerant, allowing direct connection to 5V signals. The switch is
able to pass both 0V and 5V signal levels. The HPD switch resistance depends on the input
voltage level. At low (near to 0V) input voltage levels, the resistance is 20Ω typically and at high
(near to 5V) input voltage levels, the resistance is 150Ω typically.
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2.2
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DDC channels
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The DDC channels are designed with a bi-directional NMOS gate, providing 5V signal
tolerance. The 5V tolerance allows direct connection to a standard I²C bus, thus eliminating the
need for a level shifter. When the input is a 5V, the NMOS switch is turned off and the pull up
resistor on either side of the switch determines the high voltage potential.
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5/26
STHDMI002A
Application diagram
3
Application diagram
Figure 2.
Application diagram
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STHDMI002A
4
Pin configuration
Pin configuration
Figure 3.
Pin connections
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TQFP48 (pitch = 0.5mm)
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7/26
STHDMI002A
Pin configuration
Table 1.
Pin number
Pin Name
Type
1
VCC
Power
Supply voltage (3.3V ± 5%)
2
ACLK-
Input
TMDS Clock- for port A
3
ACLK+
Input
TMDS Clock+ for port A
4
GND
Power
Ground
5
A0-
Input
TMDS Data 0- for port A
6
A0+
Input
TMDS Data 0+ for port A
7
GND
Power
Ground
8
A1-
Input
TMDS Data 1- for port A
9
A1+
Input
TMDS Data 1+ for port A
10
GND
Power
Ground
11
A2-
Input
TMDS Data 2- for port A
12
A2+
Input
TMDS Data 2+ for port A
13
VCC
Power
Supply voltage (3.3V ± 5%)
14
B_HPD
Output
15
GND
Power
16
B_DDC_SDA
I/O
17
B_DDC_SCL
18
VCC
19
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I/O
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Hot Plug Detect (HPD) output for port B
Ground
DDC SDA input for port B
DDC SCL input for port B
BCLK-
Input
TMDS Clock- for port B
BCLK+
Input
TMDS Clock+ for port B
GND
Power
Ground
B0-
Input
TMDS Data 0- for port B
23
B0+
Input
TMDS Data 0+ for port B
24
GND
Power
Ground
25
B1-
Input
TMDS Data 1- for port B
26
B1+
Input
TMDS Data 1+ for port B
27
GND
Power
Ground
28
B2-
Input
TMDS Data 2- for port B
29
B2+
Input
TMDS Data 2+ for port B
30
SEL
Input
Select control input to select port A or port B
31
Y2+
Output
TMDS Data2+ output
32
Y2-
Output
TMDS Data2- output
33
GND
Power
Ground
34
Y1+
Output
TMDS Data1+ output
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Supply voltage (3.3V ± 5%)
21
O
)-
Function
Power
20
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Pin description
Pr
STHDMI002A
Pin configuration
Table 1.
4.1
Pin description
Pin number
Pin name
Type
35
Y1-
Output
TMDS Data1- output
36
GND
Power
Ground
37
Y0+
Output
TMDS Data0+ output
38
Y0-
Output
TMDS Data0- output
39
GND
Power
Ground
40
YCLK+
Output
TMDS Clock+ output
41
YCLK-
Output
TMDS Clock- output
42
Y_DDC_SCL
I/O
DDC SCL output
43
Y_DDC_SDA
I/O
DDC SDA output
44
Y_HPD
Input
45
A_HPD
Output
46
VCC
Power
47
A_DDC_SDA
I/O
48
A_DDC_SCL
I/O
Function table
Table 2.
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Function
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Sink side hot plug detector input
High : 5V power signal asserted from source to sink
and EDID is ready
Low : No 5V power signal is asserted from source to
sink or EDID is not ready
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Hot Plug Detect (HPD) output for port A
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Supply voltage (3.3V ± 5%)
DDC SDA input for port A
DDC SCL input for port A
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Function table
Pr
Signal status
DDC Status
HPD Status
Y= TMDS Data, Clock for port A
Port B is in ‘Z’ state
Y = DDC for port A
DDC for port B is ‘Z’
Y= HPD for port A
HPD for port B is ‘Z’
Y=TMDS Data, Clock for port B
Port A is in ‘Z’ state
Y = DDC for port B
DDC for port A is ‘Z’
Y= HPD for port B
HPD for port A is ‘Z’
9/26
STHDMI002A
Maximum rating
5
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may cause
permanent damage to the device. these are stress ratings only and operation of the device at
these or any other conditions above those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relevant quality documents.
Table 3.
Absolute maximum ratings
Symbol
VCC
VI
Parameter
Value
Unit
Supply voltage to Ground
-0.5 to +4.0
V
DC Input Voltage (TMDS A,B ports)
1.7 to +4.0
V
-0.5 to +4.0
V
-0.5 to +6.0
V
-0.5 to +4.0
V
120
mA
-65 to +150
°C
300
°C
Human body model
-2 to +2
kV
Contact discharge
-2 to +2
kV
Value
Unit
TBA
°C/W
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A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL,
Y_DDC_SDA, Y_DDC_SCL, Y_HPD, A_HPD, B_HPD
VIC
DC control input voltage
IO
DC output current
TSTG
TL
VESD
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SEL
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Storage temperature
Lead temperature (10 sec)
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Pr
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Electrostatic discharge voltage on IOs(1)1
1. In accordance with the MIL STD 883 method 3015
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Table 4.
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RthJA
Thermal data
Description
Thermal Resistance Junction-ambient
STHDMI002A
6
DC electrical characteristics
DC electrical characteristics
TA = -40 to +85 °C, VCC = 3.3V ± 5%
Table 5.
DC electrical characteristics
Symbol
Parameter
Test conditions
Min
VIH
HIGH level input voltage (SEL pin)
High level guaranteed
2.0
VIL
LOW level input voltage (SEL pin)
Low level guaranteed
-0.5
VIK
Clamp Diode voltage (All IOs)
VCC = 3.465V, IIN = -18mA
IIH
Input high current (SEL pin, A, B data ports)
VCC = 3.465V, VIN = VCC
IIL
Input low current (SEL pin, A, B data ports)
VCC = 3.465V, VIN = GND
VCC = 0V;
IOFF
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Max
Unit
V
0.8
V
-1.2
V
±5
µA
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±5
µA
±5
µA
5.5
7.5
Ω
-0.8
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Outputs (Y-port) = 0V;
Inputs (A-port) = 3.465V;
Inputs (B-port) = 3.465V
Power down leakage current
Typ
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VCC = 3.135 V,
Switch ON resistance (1)
RON
VIN = 1.5 to VCC
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IIN = -40mA
RFLAT
∆RON
ON resistance flatness (1) (2)
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∆RON = RONMAX - RONMIN (1) (3)
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ON resistance match between channels
DDC I/O Pins
II(leak)
)-
Pr
Input leakage current
VCC = 3.135 V,
VIN = 1.5 to VCC
Ω
0.8
IIN = -40mA
VCC = 3.135 V,
VIN = 1.5 to VCC
1.0
1.3
Ω
0.1
+2
µA
±5
µA
IIN = -40mA
VCC = 3.465V
VI (max) = 5.3V on
isolated DDC ports
Y= 0.0V
VCC = 0V;
IOFF
Power down leakage current
CI/O
Switch off capacitance
Switch on capacitance
Outputs (Y-port) = 0V;
Inputs (A-port) = 5.3V;
Inputs (B-port) = 5.3V
VI=0V, VCC=3.3V, T= 25°C
F = 1 MHz
5
9
pF
pF
11/26
STHDMI002A
DC electrical characteristics
Table 5.
DC electrical characteristics
Symbol
Parameter
Test conditions
Min
VCC = 3.3V
IO=3mA; VO=0.0V
VCC = 3.3V
RON
IO=3mA; VO=0.4V
Switch resistance
VCC = 3.3V
IO=3mA; VO=0.8V
VCC = 3.3V
IO=3mA; VO=1.5V
Typ
II(leak)
VI (max) = 5.3V on
isolated HPD port
Y= 0.0V
Input leakage current
Ω
36
Ω
42
Ω
62
Ω
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VCC = 0V;
IOFF
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Status pins (A_HPD, B_HPD)
CI/O
RON
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Switch resistance
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0.1
(Y-port) = 0V;
(A-port) = 5.3V;
(B-port) = 5.3V
Power down leakage current
Switch off capacitance
Switch on capacitance
Pr
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VI=0V, VCC=3.3V, T= 25°C
F = 1 MHz
VCC = 3.3V
IO=3mA; VO=0.0V
VCC = 3.3V
IO=3mA; VO=5.0V
Unit
32
Status pins (Y_HPD)
VCC = 3.465V
Max
+2
µA
±5
µA
5
9
pF
pF
24
Ω
150
Ω
1. Measured by voltage drop between channels at the indicated current through the switch. On-resistance is determined by
the lower of the two voltages.
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2. Flatness is defined as the difference between the RONMAX and the RONMIN of the on resistance over the specified range.
3. ∆RON measured at the same VCC, temperature and voltage level.
12/26
STHDMI002A
6.1
DC electrical characteristics
Capacitance
TA = 25°C, f = 1MHz
Table 6.
Capacitance
Symbol
CIN
1.
Parameter
Test conditions
Min
Typ
Max
Unit
Input capacitance
VIN = 0V
2
3
pF
COFF
Port x0 to Port x1, Switch off (Note 4)
VIN = 0V
4
6
pF
CON
Capacitance switch on (x to x0 or x to x1) (1)
VIN = 0V
6
12
pF
x = Port Y; x0 = Port A; x1 = Port B
6.2
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Power supply characteristics
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TA = -40 to +85 °C
Table 7.
Symbol
ICC
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Power supply characteristics
Parameter
Quiescent power supply current
Test conditions
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VCC = 3.465 V,
Min
VIN = VCC or GND
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6.3
Dynamic electrical characteristics
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Typ
Max
Unit
50
500
µA
Typ
Max
Unit
TA = -40 to +85 °C, VCC = 3.3V ± 5%
Table 8.
Dynamic electrical characteristics
Symbol
XTALK
OIRR
Parameter
Non-adjacent channel Cross-talk
Off Isolation
Test conditions
Min
RL = 100Ω, f = 370MHz
-32
dB
RL = 100Ω, f = 825MHz
-31
dB
RL = 100Ω, f = 370MHz
-36
dB
RL = 100Ω, f = 825MHz
-30
dB
BW
-3dB bandwidth
850
MHz
DR
Data rate per channel
1.65
Gbps
13/26
STHDMI002A
DC electrical characteristics
6.4
Dynamic switching characteristics
TA = -40 to +85 °C, VCC = 3.3V ± 5%
Table 9.
Dynamic switching characteristics
Symbol
tPD
Parameter
Test conditions
Min
VCC = 3.135V to 3.465V
Propagation delay
Typ
Max
0.30
Unit
ns
tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
0.5
6.5
9
ns
tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
0.5
6.5
8.5
ns
0.2
ns
0.2
ns
2.5
ns
tSK(O)
Output skew between center port to any
other port
VCC = 3.135V to 3.465V
0.1
tSK(P)
Skew between opposite transition of the
same output (tPHL - tPLH)
VCC = 3.135V to 3.465V
0.1
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DDC I/O pins
Propagation delay from A_DDC_SDA/
B_DDC_SDA to Y_DDC_SDA or
A_DDC_SCL/B_DDC_SCL to
tPD(DDC)
Y_DDC_SCL or
Y_DDC_SDA to A_DDC_SDA/
B_DDC_SDA
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let
CL = 10pF
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)
tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
6.5
9
ns
tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
6.5
8.5
ns
2.5
ns
s
(
t
c
Status pins (Y_HPD, A_HPD, B_HPD)
tPD(HPD)
du
Propagation delay (from Y_HPD to the
active port of HPD)
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P
CL = 10pF
tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
6.5
9
ns
tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1
VCC = 3.135V to 3.465V
6.5
8.5
ns
Typ
Max
Unit
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Note:
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6.5
Table 10.
Symbol
ESD
14/26
x = Port Y; x0 = Port A; x1 = Port B
ESD performance
ESD performance
Parameter
MIL STD 883 method 3015 (all pins)
Test conditions
Human Body Model (HBM)
Min
±2
kV
STHDMI002A
7
Test circuit for electrical characteristics
Test circuit for electrical characteristics
Figure 4.
Timing measurement test circuit
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Note: 1 CL = Load capacitance: includes jig and probe capacitance.
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2 RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Figure 5.
Bandwidth measurement test circuit
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Note:
CL includes probe and jig capacitance
Frequency response is measured at the output of the ON channel. For example, when
VSEL = 0 and Y0+ is the input, the output is measured at A0+. All unused analog I/O ports are
left open.
HP8753ES set up:
Average = 4
RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
15/26
STHDMI002A
Test circuit for electrical characteristics
Figure 6.
Crosstalk measurement test circuit
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Note: 1 CL includes probe and jig capacitance
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2 A 50Ω termination resistor is needed to match the loading network analyzer
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Crosstalk is measured at the output of the non-adjacent ON channel. For example, when
VSEL = 0, and Y0- is the input, the output is measured at Y1-. All unused analog input ports (Y)
are connected to GND and output ports (A,B) are left open.
HP8753ES set up:
Average = 4
RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
16/26
STHDMI002A
Figure 7.
Test circuit for electrical characteristics
Off-isolation measurement test circuit
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Note: 1 CL includes probe and jig capacitance
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2 A 50Ω termination resistor is needed to match the loading network analyzer
Off-isolation is measured at the output of the OFF channel. For example, when VSEL=0, and
Y0- is the input, the output is measured at B0-. All unused analog input ports (Y) are connected
to GND and output ports (A,B) are left open.
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HP8753ES set up:
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Average = 4
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RBW = 3kHz
VBIAS = 0.35V
ST = 2s
P1 = 0dBm
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STHDMI002A
Timing waveforms
8
Timing waveforms
Figure 8.
Propagation delay times
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Figure 9.
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Enable and disable times
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STHDMI002A
Timing waveforms
Figure 10. Output skew
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Figure 11. Pulse skew
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STHDMI002A
Application information
9
Application information
9.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended
to always apply VCC before applying any signals to the input/output or control pins.
9.2
Supply bypassing
Bypass each of the VCC pins with 0.1µF and 1nF capacitors in parallel as close to the device as
possible, with the smaller-valued capacitor as close to the VCC pin of the device as possible.
9.3
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Differential traces
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The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the connectors
and the device.
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a)
Maintain 100-Ω differential transmission line impedance into and out of the
STHDMI002A.
b)
Keep an uninterrupted ground plane below the high-speed I/Os.
c)
Keep the ground-path vias to the device as close as possible to allow the shortest
return current path.
d)
Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
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Output trace characteristics affect the performance of the STHDMI002A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance and
termination resistor. Run the differential traces close together to minimize the effects of the
noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the
differential trace layout. Avoid 90 degree turns and minimize the number of vias to further
prevent impedance discontinuities.
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STHDMI002A
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect . The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
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STHDMI002A
Package mechanical data
Figure 12. TQFP48 package dimensions
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STHDMI002A
Package mechanical data
Figure 13. TQFP48 Tape and reel dimensions
Tape & Reel TQFP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
330
MAX.
C
12.8
D
N
12.992
13.2
0.504
0.519
20.2
0.795
60
2.362
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9.5
9.7
0.374
Bo
9.5
9.7
0.374
Ko
2.1
2.3
0.083
Po
3.9
4.1
P
11.9
12.1
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Pr
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0.882
0.382
0.382
0.091
0.153
0.161
0.468
0.476
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STHDMI002A
Order codes
11
Order codes
Table 11.
Order codes
Part number
Temperature range
Package
Packing
STHDMI002ABTR
–65° C to +150° C
TQFP48
Tape and reel
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STHDMI002A
12
Revision history
Revision history
Table 12.
Revision history
Date
Revision
10-Oct-2006
1
Change
First release
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STHDMI002A
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
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