STHVDAC-303F6

STHVDAC-303 High voltage BST capacitance controller Datasheet  production data Features ■ Dedicated ASIC to control BST tunable capacitances ■ Operation compliant with cellular systems requirements ■ Integrated boost converter with 3 programmable outputs (from 0 to 30 V) ■ Low power consumption ■ 3-wire serial interface (30 or 32 bit SPI) ■ Available in WLCSP for stand-alone or SiP module integration ■ RF tunable passive implementation in mobile phones to optimize the radiated performances Lead-free, Flip Chip (16 bumps) Figure 1. Pin configuration (bump view) A4 A3 A2 A1 B4 B3 B2 B1 Application C4 C3 C2 C1 ■ Cellular antenna tunable matching network in multi-band GSM/WCDMA mobile phone D4 D3 D2 D1 ■ Compatible with open loop antenna tuner applications Description The ST BST capacitance controller STHVDAC-303 is a high voltage digital to analog converter (DAC), specifically designed to control and meet the wide tuning bias voltage requirement of the BST tunable capacitances. It provides 3 independent high voltage outputs, thus having the capability to control 3 different capacitances in parallel. It is fully controlled through a 3-wire serial interface. BST capacitances are tunable capacitances intended for use in mobile phone application, and dedicated to RF tunable applications. These tunable capacitances are controlled through a bias voltage ranging from 0 to 30 V. The implementation of BST tunable capacitance in mobile phones enables significant improvement in terms of radiated performance, making the performance almost insensitive to the external environment. November 2012 This is information on a product in full production. Doc ID 18317 Rev 3 1/24 www.st.com 24 Contents STHVDAC-303 Contents 1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 HVDAC output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 3-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Power-up / down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 Settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.7 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 Timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Serial interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Serial interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 Ordering information schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 Doc ID 18317 Rev 3 STHVDAC-303 Electrical characteristics 1 Electrical characteristics Table 1. Absolute maximum ratings (limiting value) Symbol Parameter Rating Unit AVDD Analog supply voltage -0.3 to +5.5 V Vdig Digital supply voltage -0.3 to +3.3 V VI/O Input voltage logic lines (DATA, CLK, CS) -0.5 to Vdig + 0.5 V 2 kV 500 V -55 to +150 °C 150 °C VESD (HBM) Human body model, JESD22-A114-B, All I/O VESD (CDM) Charge device model, JESD22-C101-C, All I/O Tstg Tj Table 2. Storage temperature range Maximum junction temperature Recommended operating conditions Rating Symbol Parameter Unit Min. Typ. Max. Operating ambient temperature -25 - +85 °C AVDD Analog supply voltage 2.3 - 5 V Vdig Digital supply voltage 1.7 - 3 V VIH Input voltage logic level HIGH (DATA, CLK, CS) 0.7*Vdig - Vdig + 0.3 V VIL Input voltage logic level LOW (DATA, CLK, CS) -0.3 - 0.35*Vdig V TAMB_oP Doc ID 18317 Rev 3 3/24 Electrical characteristics Table 3. STHVDAC-303 DC characteristics Conditions: AVdd from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C unless otherwise specified Symbol Parameter Conditions Min. Typ.(1) Max. Unit 5 µA 1 mA Shutdown mode, CS level LOW 10 µA Active Mode: (3 outputs active) CS LOW CS HIGH, FCLK = 13 MHz CS HIGH, FCLK = 26 MHz 0.2 0.6 1 Shutdown mode IDD AVDD supply current Active mode (3 outputs active) 0.67 Idig Vdig supply current IIH Input current logic level HIGH Any mode, DATA, CLK, CS pins -2 2 µA IIL Input current logic level LOW Any mode, DATA, CLK, CS pins -2 2 µA Max. Unit mA 1. Typical value with typical application condition, VHV = 20 V, AVDD = 3.3 V, 25 °C, Iload = 3*1µA Table 4. Boost converter characteristics Conditions: AVDD from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C unless otherwise specified) Symbol Parameter Conditions Min. Typ. Vhv_low Minimum programmable output voltage Active mode, DAC_boost = 0h 15 V Vhv_high Maximum programmable output voltage Active mode, DAC_boost = Fh 30 V Resolution Boost voltage resolution 4 bits DAC 1 V DAC boost error DAC A, DAC B, DAC C and DAC_boost settings according to Table 6. Error 4/24 Doc ID 18317 Rev 3 -6 +6 %Vout STHVDAC-303 Table 5. Electrical characteristics High voltage DAC output characteristics Conditions: AVDD from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C, OUTA, OUTB, OUTC, unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit SHUTDOWN MODE Zout OUTA, OUTB, OUTC output impedance 7 M 26.5 V ACTIVE MODE VOH OUTA, OUTB, OUTC maximum output voltage DAC A = DAC B = DAC C = FFh DAC_boost = Fh, IOH < 10 µA VOL OUTA, OUTB, OUTC minimum output voltage DAC A = DAC B = DAC C = 01h DAC_boost from 0h to Fh IOL < 10 µA 2 V RPD OUTA, OUTB, OUTC set in pull down mode DAC A = DAC B = DAC C = 00h DAC_boost from 0h to Fh 500  Voltage resolution / OUTA, OUTB, OUTC 8 bits DAC, full range 30 V Zero scale offset DAC A, DAC B, DAC C and DAC_boost settings according to Table 6. -2 +2 LSB INL Integral non linearity DAC A, DAC B, DAC C and DAC_boost settings according to Table 6. -3 +3 LSB DNL Differential non linearity DAC A, DAC B, DAC C and DAC_boost settings according to Table 6. -0.5 +0.5 LSB gain Gain error DAC A, DAC B, DAC C and DAC_boost settings according to Table 6. -6 +6 %Vout Over current protection Any DAC output 50 mA Resolution Voffset Isc Doc ID 18317 Rev 3 117.64 mV 5/24 Electrical characteristics Table 6. STHVDAC-303 Recommended settings for DAC outputs and DAC_boost Conditions: AVDD from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C, OUTA, OUTB, OUTC, unless otherwise specified Symbol DACMIN DACMAX VDACtyp 6/24 Parameter Conditions Min. Minimum DAC setting DAC_boost from 0H to FH 13h Maximum DAC setting DAC_boost = 0h DAC_boost = 1h DAC_boost = 2h DAC_boost = 3h DAC_boost = 4h DAC_boost = 5h DAC_boost = 6h DAC_boost = 7h DAC_boost = 8h DAC_boost = 9h DAC_boost = Ah DAC_boost = Bh DAC_boost = Ch DAC_boost = Dh DAC_boost = Eh DAC_boost = Fh Typical DAC output voltage DAC_boost = 0h, DACx = DACMAX DAC_boost = 1h, DACx = DACMAX DAC_boost = 2h, DACx = DACMAX DAC_boost = 3h, DACx = DACMAX DAC_boost = 4h, DACx = DACMAX DAC_boost = 5h, DACx = DACMAX DAC_boost = 6h, DACx = DACMAX DAC_boost = 7h, DACx = DACMAX DAC_boost = 8h, DACx = DACMAX DAC_boost = 9h, DACx = DACMAX DAC_boost = Ah, DACx = DACMAX DAC_boost = Bh, DACx = DACMAX DAC_boost = Ch, DACx = DACMAX DAC_boost = Dh, DACx = DACMAX DAC_boost = Eh, DACx = DACMAX DAC_boost = Fh, DACx = DACMAX Doc ID 18317 Rev 3 Typ. Max. Unit - 5Dh 65h 6Dh 75h 7Dh 85h 8Dh 95h 9Dh A5h ADh B5h BDh C5h CDh D5h 10.90 11.84 12.77 13.71 14.65 15.59 16.52 17.46 18.40 19.34 20.27 21.21 22.15 23.09 24.02 24.96 - V STHVDAC-303 2 Functional block diagram Functional block diagram Figure 2. HVDAC functional block diagram Boost diode B4 A3 Boost power MOS sense drive Boost control ref A4 4-bit DAC VHV C4 8-bit ref DAC “A” Internal biasing reference D4 VHV Power sense management and control sense logic C1 A1 B1 8-bit ref DAC “B” HVAMP D2 GND_REF POR_VDIG A2 VHV Serial interface and register bank 8-bit ref DAC “C” AVDD B3 Table 7. D1 GND_REF C2 B2 HVAMP HVAMP D3 GND_REF C3 Signal descriptions Pin number Pin name Description A1 DATA Serial interface / Serial DATA A2 Vdig Digital supply A3 VHV Boost high voltage output A4 GND_BOOST Ground B1 CS Serial interface / Chip select B2 TEST Test pin / connected to GND in final application B3 GND_DIG Ground B4 IND_BOOST Boost inductance C1 CLK Serial interface / Serial clock C2 GND_REF Analog ground C3 AVDD Analog supply C4 AVDD Analog supply D1 OUTA High voltage output A D2 OUTB High voltage output B D3 OUTC High voltage output C D4 Rbias Biasing reference resistance Doc ID 18317 Rev 3 7/24 Theory of operation STHVDAC-303 3 Theory of operation 3.1 HVDAC output voltages The HVDAC outputs are directly controlled by programming the 8-bit DAC (DAC A, DAC B and DAC C) through the 3-wire serial interface. The DAC stages are driven from a reference voltage, generating an analog output voltage driving a high voltage amplifier supplied from the boost converter (see HVDAC block diagram - Figure 2). The HVDAC output voltages are scaled from 0 to 30 V, with 255 steps of 117 mV (30/255 = 0.11764 V). The nominal HVDAC output can be approximated to 117 mV x (DAC value). For performance optimization, it is also possible to control the boost output voltage (VHV) from 15 V to 30 V, by programming the DAC_boost value (4 bits / 1 V step). For proper operation, ST recommends the operation of the HVDAC outputs 2 V below the actual boost output voltage (VHV), to avoid clamping the HVDAC outputs to the boost output voltage. Recommended settings for DAC A, DAC B and DAC C according to DAC_boost settings are described in Table 6., considering the overall HVDAC accuracy. These recommended settings are further described on Figure 5 Minimum HVDAC output voltage is also limited to 2 V, meaning minimum DAC command is equal to 19 (or 13h), independent of the DAC_boost setting. DAC settings can be programmed outside this recommended operating range, but in this case the HVDAC performance (accuracy and noise) be outside the specified range. If DAC value is set to 00 h, then the corresponding output is directly connected to GND through a pull-down resistor (500 ). Figure 3. Recommended DAC commands versus DAC_boost setting 256 30 230 27 205 24 179 21 154 18 128 15 102 12 77 9 51 6 26 3 0 0 0 1 2 3 4 5 6 7 8 9 10 DAC_boost command 8/24 Doc ID 18317 Rev 3 11 12 13 14 15 Typ. DAC output voltage (V) Max DAC command (dec) Max DAC command and output voltage STHVDAC-303 3.2 Theory of operation Operating modes The following operating modes are accessible through the serial interface: 3.3 ● Shutdown mode: The HVDAC is switched off, and all the blocks in the control ASIC are switched off. Power consumption is almost zero in this mode, the DAC outputs are in high Z state. The shutdown mode is set by sending a dedicated command through the serial interface. ● Active mode: The HVDAC is switched on and the DAC outputs are fully controlled through the serial interface. The DAC settings can be dynamically modified and the HV outputs will be adjusted according to the specified timing diagrams. Each DAC can be individually controlled and/or switched off according to application requirements. This mode is set and controlled through serial interface commands. Power-on reset Power-on reset is implemented on the Vdig supply input, ensuring the HVDAC will be reset to default mode once Vdig supply line rises above a given threshold (typically 1 V). This trigger will force all registers to their default value. 3.4 3-wire serial interface The HVDAC is fully controlled through a 3-wire serial interface (DATA, CS, CLOCK).This interface is further described in the next sections of this document. 3.5 Power-up / down sequence Table 8 and Figure 5 describe the HVDAC settling time requirements and recommended timing diagrams. Switching from shutdown to active mode is triggered by sending a dedicated serial interface command. Switching from active to shutdown mode will occur after sending the related command through the 3-wire serial interface. Active mode can be directly activated from shutdown. In any case the HVDAC will be operational only after Tactive (max 300 µs). A settling time (Tset) is required following each DAC command in active mode. During this settling time the HVDAC output voltages will vary from the initial to the updated DAC command. 3.6 Settling time The ST HVDAC will set the bias voltage of the tuner within 35 µs after the chip select is released. The setting time is defined as the time it takes for the output to reach 95% of its final value. A positive setting time (Tset +) is defined when the output voltage rises and a negative setting time (Tset -) when it decreases to its final value. See Figure 4 for details. Doc ID 18317 Rev 3 9/24 Theory of operation Figure 4. STHVDAC-303 Bias voltage of the tuner CS time 95% Vout time Tset+ 95% Tset- 3.7 Vout time Power supply sequencing The ST HVDAC does not require any specific power supply sequencing. It is assumed that the AVDD input will be directly supplied from the battery and will then be the first on. If Vdig supply is pulsed, 5 µs are required (max) to settle internal voltages before sending the first command through the 3-wire serial interface. 10/24 Doc ID 18317 Rev 3 STHVDAC-303 3.8 Theory of operation Timing parameters Table 8. Timing parameters Conditions: AVDD from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C, OUTA, OUTB, OUTC, unless otherwise specified Symbol Parameter Conditions Internal voltages activation time from shutdown to active mode Chv = 22 nF, DAC_boost = 07h max. Unit 300 µs Tactive Activation time Tset+ Chv = 22 nF, DAC boost 07h, Vout 00h to 88h Output positive setting (worst-case), equivalent load of 15 k and 1 time @ 95% nF 35 µs Tset- Output negative setting time @ 95% 35 µs Figure 5. Chv = 22 nF, DAC boost 07h, Vout 88 h to 13 h, equivalent load of 15 k and 1 nF Timing diagram example Operating mode Shut down OUTx V HV Shut down Active Undefined settling steady steadystate, According to settling DAC settings steady state, According to DAC settings undefined Steady State settling I dd Idig CS ACTIVE command DAC C DACx command DAC A&B DACx command SHUTDOWN command DATA Tactive Tset Doc ID 18317 Rev 3 Tset 11/24 Register table 4 STHVDAC-303 Register table The HVDAC embeds 5 x 16-bit registers. Registers content is described in Table 9. Registers 1 to 3 are used to control the mode of operations and the HVDAC settings. HVDAC control and settings are thus fully ensured by programming these three registers. Registers 4 and 5 are reserved for test purpose, and should not be addressed. Table 9. Reg # 12/24 Register table Access Size type (bits) Used to set up OUT C W 16 DAC control DATA register #2 Used to set up OUT A and B W 16 DAC control Mode register Used to set up the operating modes W 16 Name Purpose 1 DAC control DATA register #1 2 3 4 Reserved 5 Reserved Doc ID 18317 Rev 3 STHVDAC-303 5 Serial interface specification Serial interface specification Table 10. Interface specification Conditions: AVDD from 2.3 to 5 V, Vdig from 1.7 to 3 V, Tamb from -25 °C to +85 °C, unless otherwise specified Symbol Parameter FCLK Clock frequency TCLK Clock period THIGH Conditions Min. Typ. Max. Unit 26 MHz 38.4 ns Clock high time 13 ns TLOW Clock low time 13 ns NBIT SPI telegram length STHVDAC-303Ix6 30 bits NBIT SPI telegram length STHVDAC-303x6 32 bits TCSsetup CS setup time 70% of rising edge of CS to 30% of rising edge of first clock cycle 5 ns TCShold CS hold time 30% of falling edge of last CLK cycle to 70% of falling edge of CS 5 ns TDsetup DATA setup time Relative to 30% of CLK rising edge 4 ns TDhold DATA hold time Relative to 70% of CLK rising edge 4 ns CCLK CLK pin input capacitance VOSC = 30 mV, F = 1 MHz CDATA CCS 5 pF DATA pin input capacitance 5 pF CS pin input capacitance 5 pF Doc ID 18317 Rev 3 13/24 Serial interface specification STHVDAC-303 In Figure 6: 3-wire serial interface description the data is presented on the falling edge of CLK, and latched on the rising edge of CLK. Command is latched on the falling edge of CS. Figure 6. 3-wire serial interface description 30 bit interface DATA A13 A15 A12 A13 A11 A14 A2 A1 A0 D15 D14 D13 D2 D1 D0 CLOCK CLOCK CS 70% DATA A13 A12 D1 D0 30% THIGH Tdhold TDsetup CLOCK 70% 70% TLOW 30% TCLK TCShold TCSsetup 70% 70% CS 32 bit interface DATA A15 A14 A13 A2 A1 A0 D15 D14 D13 D2 D1 D0 CLOCK CLOCK CS 70% DATA A15 A14 D1 D0 30% THIGH Tdhold TDsetup CLOCK 70% 70% TLOW 30% TCLK TCShold TCSsetup 70% 70% CS 14/24 Doc ID 18317 Rev 3 STHVDAC-303 Serial interface frame structure 6 Serial interface frame structure Table 11. 30-bit frame address decoding A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 1 0 0 1 0 0 X X X X X Fixed Tuner Table 12. Device ID Register address for operation 32-bit frame address decoding A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 0 1 0 1 0 0 1 0 0 X X X X X Fixed Table 13. Tuner Device ID Register address for operation Register decoding Command A4 A3 A2 A1 A0 #1 0 0 0 0 0 #2 0 0 0 0 1 #3 1 0 0 0 0 Mode selection #4 1 1 0 0 0 Reserved #5 1 0 0 1 0 Reserved Table 14. DATA reserved DAC C DAC B DAC A Data decoding for data register [00000] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved Table 15. DAC C Data decoding for data register [00001] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DAC B Table 16. DAC A Data decoding for mode selection register [10000] D15 D14 D13 D12 0 0 0 1 D11 D10 D9 D8 DAC_BOOST D7 D6 D5 D4 D3 D2 D1 D0 0 0 DAC A DAC B DAC C 0 Mode Doc ID 18317 Rev 3 15/24 Serial interface frame structure Table 17. D11 STHVDAC-303 HV-DAC mode selection - Register [10000] D10 D9 D8 D7 DAC boost D6 Mode D3 D2 D1 Comments DAC A DAC B DAC C 0 0 0 0 x x x VHV = 15V 0 0 0 1 x x x VHV = 16V 0 0 1 0 x x x VHV = 17V 0 0 1 1 x x x VHV = 18V 0 1 0 0 x x x VHV = 19V 0 1 0 1 x x x VHV = 20V 0 1 1 0 x x x VHV = 21V 0 1 1 1 x x x VHV = 22V Active mode 1 0 0 0 x x x VHV = 23V 1 0 0 1 x x x VHV = 24V 1 0 1 0 x x x VHV = 25V 1 0 1 1 x x x VHV = 26V 1 1 0 0 x x x VHV = 27V 1 1 0 1 x x x VHV = 28V 1 1 1 0 x x x VHV = 29V 1 1 1 1 x x x VHV = 30V x x x x 0 0 x x x Shutdown mode x x x x 0 1 x x x reserved x x x x 1 0 x x x Active mode x x x x 1 1 x x x reserved x x x x 1 0 0 0 0 x x x x 1 0 1 1 1 Table 18. D11 HVDAC mode selection default settings - Register [10000] D10 D9 D8 D7 DAC boost 0 16/24 Active mode / DAC Any DAC outputs outputs in combination high Z-state possible, as Active mode described in / DAC Table 6. outputs enabled 0 D6 Mode 0 0 0 Doc ID 18317 Rev 3 0 D3 D2 D1 DAC A DAC B DAC C 0 0 0 STHVDAC-303 Table 19. Serial interface frame structure Data registers [00000] default settings D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Table 20. DAC C Data registers [00001] default settings D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC B DAC A Doc ID 18317 Rev 3 17/24 Application schematic 7 STHVDAC-303 Application schematic Figure 7. Recommended application schematic Vdig Cdig Chv A1 A2 DATA VDIG B2 GND B1 CS A3 A4 VHV GND_BOOST GND B3 IND_BOOST B4 ST HVDAC 3 wires serial I/F Lboost Rfilt Cboost C1 CLK AVDD C4 Vbat Cbias C2 GND_REF BST ca p AVDD OUTA OUTB OUTC RBIAS D1 D2 D3 D4 C3 BST cap Rbias CdecA BST cap CdecB OUT3 OUT2 OUT1 Recommended PCB layout VBAT Figure 8. CdecC CLK CS DATA Vdig 18/24 Doc ID 18317 Rev 3 STHVDAC-303 Table 21. Component Application schematic Recommended external BOM Description Cboost Boost supply capacitor Lboost Boost inductance Nominal Package Package value (inch) (mm) 1 µF Recommended P/N 0402 1005 Murata: GRM155R60J105KE19D 0603 1608 COILCRAFT: 0603LS-153XGL 2014 ABCO: LPS181210T-150M 15 µH Rfilt Decoupling resistor, 5% 3.3  0402 1005 Vishay: CRCW04023R30JNED Cdig Digital supply decoupling 100 nF 0402 1005 Murata: GRM155R71C104KA88D Cbias Analog supply decoupling 1 µF 0402 1005 Murata: GRM155R60J105KE19D Rbias Reference bias resistor, 1% 110 k 0201 0603 Multicomp: MCRE000189 Chv Boost output capacitance, 50 V 22 nF 0402 1005 Murata: GRM155R71H223KA12 Semco: CL21B223KBCNNNC Cdec Decoupling capacitance, 50 V 100 pF 0201 0603 TDK: C0603COG1H101J Doc ID 18317 Rev 3 19/24 Ordering information schemes 8 STHVDAC-303 Ordering information schemes Figure 9. Ordering information scheme for 30-bit serial peripheral interface STHVDAC 30 3 I - x6 High voltage DAC Voltage 30 = 30V max Vout Output lines 3 = 3 output lines Serial peripheral interface I = 30 bit Package F6 = Flip Chip, 500 µm pitch C6 = Flip Chip, 500 µm pitch with coating Figure 10. Ordering information scheme for 32-bit serial peripheral interface STHVDAC High voltage DAC Voltage 30 = 30V max Vout Output lines 3 = 3 output lines Package F6 = Flip Chip, 500 µm pitch C6 = Flip Chip, 500 µm pitch with coating 20/24 Doc ID 18317 Rev 3 30 3 - x6 STHVDAC-303 Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. Package dimensions Figure 12. Footprint 0.293 ± 0.010 mm 2.086 mm ± 50 µm 600 µm ± 40 650 µm ± 40 2.086 mm ± 50 µm 250 µm ± 30 500 µm ± 50 500 µm ± 50 9 Package information Non-coated Coated Figure 13. Marking Copper pad diameter: 220 µm recommended 260 µm maximum Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) Solder mask opening: 300 µm minimum ECOPAK grade Solder stencil opening: 220 µm recommended Doc ID 18317 Rev 3 x x z y ww 21/24 Ordering information STHVDAC-303 Figure 14. Tape and reel specification Dot identifying Pin A1 location 2.0 Ø 1.55 4.0 xxz yww ST xxz yww 2.22 ST xxz yww ST 8.0 3.5 2.22 1.75 0.22 4.0 0.73 All dimensions are typical values in mm 10 Ordering information Table 22. Note: 22/24 User direction of unreeling Ordering information Order code SPI Marking Package Weight STHVDAC-303IF6 30 bits PC Flip Chip 5 mg STHVDAC-303IC6 30 bits PE Coated Flip Chip 5.3 mg STHVDAC-303F6 32 bits PA Flip Chip 5 mg STHVDAC-303C6 32 bits PD Coated Flip Chip 5.3 mg Base qty Delivery mode 5000 Tape and reel More information is available in the STMicroelectronics Application note: AN1235: “Flip Chip: Package description and recommendations for use” Doc ID 18317 Rev 3 STHVDAC-303 11 Revision history Revision history Table 23. Document revision history Date Revision Changes 14-Mar-2011 1 Initial release. 04-Apr-2012 2 Corrected typographical error in Application. 05-Nov-2012 3 Updated document status. Doc ID 18317 Rev 3 23/24 STHVDAC-303 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 24/24 Doc ID 18317 Rev 3