STI6N90K5

STI6N90K5 N-channel 900 V, 0.91 Ω typ., 6 A MDmesh™ K5 Power MOSFET in an I²PAK package Datasheet - production data Features TAB 1 2      3 I²PAK Order code VDS RDS(on) max. ID STI6N90K5 900 V 1.10 Ω 6A Industry’s lowest RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STI6N90K5 6N90K5 I²PAK Tube November 2016 DocID029949 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STI6N90K5 Contents 1 Electrical ratings ............................................................................... 3 2 Electrical characteristics ................................................................. 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ...................................................................................... 8 4 Package information ........................................................................ 9 4.1 5 2/12 I²PAK package information ............................................................... 9 Revision history .............................................................................. 11 DocID029949 Rev 1 STI6N90K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ± 30 V ID Drain current (continuous) at TC = 25 °C 6 A ID Drain current (continuous) at TC = 100 °C 4 A Drain current (pulsed) 24 A W ID(1) PTOT Total dissipation at TC = 25 °C 110 dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range Tstg Storage temperature range - 55 to 150 V/ns °C Notes: (1)Pulse (2)I SD (3)V width limited by safe operating area ≤ 6 A, di/dt ≤ 100 A/μs; VDS peak < V(BR)DSS, VDD = 450 V. DS ≤ 720 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 1.14 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Value Unit 2 A 210 mJ Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) DocID029949 Rev 1 3/12 Electrical characteristics 2 STI6N90K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 900 Typ. Max. Unit V VGS = 0 V, VDS = 900 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 900 V TC = 125 °C(1) 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3 A ±10 µA 4 5 V 0.91 1.10 Ω Min. Typ. Max. Unit - 342 - pF - 31 - pF - 1.2 - pF - 55 - pF - 20 - pF 6.4 - Ω 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related VDS = 0 to 720 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - VDD = 720 V, ID = 6 A VGS= 10 V (see Figure 15: "Test circuit for gate charge behavior") - 11 - nC - 2.5 - nC - 7 - nC Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Notes: (1) Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. (2) Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 4/12 DocID029949 Rev 1 STI6N90K5 Electrical characteristics Table 7: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off delay time tf Fall time Test conditions Min. Typ. Max. Unit VDD= 450 V, ID = 3 A, RG = 4.7 Ω VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 12.4 - ns - 12.2 - ns - 30.4 - ns - 15.5 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol Parameter Test conditions ISD Source-drain current - 6 A ISDM(1) Source-drain current (pulsed) - 24 A VSD(2) Forward on voltage - 1.5 V ISD = 6 A, VGS = 0 V trr Reverse recovery time Qrr Reverrse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 342 ns - 3.13 µC - 18.3 A - 536 ns - 4.42 µC - 16.5 A Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage Test conditions Min. Typ. Max. Unit IGS = ± 1 mA,ID = 0 A 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID029949 Rev 1 5/12 Electrical characteristics 2.1 STI6N90K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance CG20930 K δ = 0.5 δ = 0.2 δ = 0.1 10-1 Z Zthth == kk R Rthj-C thj-C δδ == ttp // Ƭ Ƭ p δ = 0.05 δ = 0.02 δ = 0.01 tp SINGLE PULSE 10-2 10-5 6/12 10-4 10-3 10-2 ƬƬ 10-1 tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID029949 Rev 1 STI6N90K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs starting TJ Figure 13: Source-drain diode forward characteristics DocID029949 Rev 1 7/12 Test circuits 3 STI6N90K5 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior VDD RL IG= CONST VGS + pulse width 2200 μF 100 Ω D.U.T. 2.7 kΩ VG 47 kΩ 1 kΩ AM01469v10 8/12 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID029949 Rev 1 STI6N90K5 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 I²PAK package information Figure 20: I²PAK package outline DocID029949 Rev 1 9/12 Package information STI6N90K5 Table 10: I²PAK package mechanical data mm Dim. 10/12 Min. Typ. Max. A 4.40 – 4.60 A1 2.40 – 2.72 b 0.61 – 0.88 b1 1.14 – 1.70 c 0.49 – 0.70 c2 1.23 – 1.32 D 8.95 – 9.35 e 2.40 – 2.70 e1 4.95 – 5.15 E 10 – 10.40 L 13 – 14 L1 3.50 – 3.93 L2 1.27 – 1.40 DocID029949 Rev 1 STI6N90K5 5 Revision history Revision history Table 11: Document revision history Date Revision 02-Nov-2016 1 DocID029949 Rev 1 Changes First release. 11/12 STI6N90K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID029949 Rev 1