STIPNS1M50T-H

STIPNS1M50T-H Datasheet SLLIMM-nano IPM, 3-phase inverter, 1 A, 3.6 Ω max., 500 V MOSFET Features 16 • 17 1 26 NSDIP-26L • • • • • • • • • • • IPM 1 A, 500 V, RDS(on) = 3.6 Ω, 3-phase MOSFET inverter bridge including control ICs for gate driving Optimized for low electromagnetic interference 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/ pull-up resistors Undervoltage lockout Internal bootstrap diode Interlocking function Shutdown function Comparator for fault protection against overcurrent Op-amp for advanced current sensing Optimized pinout for easy board layout NTC for temperature control (UL 1434 CA 2 and 4) Moisture sensitive level (MSL) 3 for SMD package Applications • • 3-phase inverters for small power motor drives Roller shutters, dishwashers, refrigerator fans, air-conditioning fans, draining and recirculation pumps Description Product status link STIPNS1M50T-H Product summary Order code STIPNS1M50T-H Marking IPNS1M50T-H Package NSDIP-26L Packing Tape and reel This SLLIMM (small low-loss intelligent molded module) nano provides a compact, high-performance AC motor drive in a simple, rugged design. It is composed of six MOSFETs and three half-bridge HVICs for gate driving, providing low electromagnetic interference (EMI) characteristics with optimized switching speed. The package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. This IPM includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. SLLIMM is a trademark of STMicroelectronics. DS12106 - Rev 3 - August 2019 For further information contact your local STMicroelectronics sales office. www.st.com STIPNS1M50T-H Internal schematic diagram and pin configuration 1 Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram (26)N W GND(1 ) T/SD/OD (2) NTC VccW(3 ) HinW(4 ) (25)W,OUT W GND HVG VCC HIN OUT (24)Vboot W LVG SD/OD LinW(5 ) LIN Vboot OP+(6 ) (23)N V OPOUT(7 ) GND OP+ OPOUT OP-(8 ) OP- VCC VccV(9 ) HIN HVG (22)V,OUT V OUT LVG SD/OD HinV(10) LIN Vboot (21)Vboot V LinV(11 ) Cin(12) GND CIN (20)N U HVG VccU(13 ) VCC HinU(14) HIN OUT (19)U,OUT U LVG SD/OD LIN Vboot (18) P T/SD/OD(15) LinU(16 ) (17)Vboot U GIPD120120170806SA DS12106 - Rev 3 page 2/23 STIPNS1M50T-H Internal schematic diagram and pin configuration Table 1. Pin description DS12106 - Rev 3 Pin Symbol Description 1 GND 2 T/SD/OD 3 VCC W Low voltage power supply W phase Ground NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) 4 HIN W High-side logic input for W phase 5 LIN W Low-side logic input for W phase 6 OP+ 7 OPOUT 8 OP- 9 VCC V Low voltage power supply V phase 10 HIN V High-side logic input for V phase 11 LIN V Low-side logic input for V phase 12 CIN 13 VCC U Low voltage power supply for U phase 14 HIN U High-side logic input for U phase 15 T/SD/OD 16 LIN U 17 VBOOT U 18 P 19 U, OUTU 20 NU Negative DC input for U phase 21 VBOOT V Bootstrap voltage for V phase 22 V, OUTV V phase output 23 NV Negative DC input for V phase 24 VBOOT W Bootstrap voltage for W phase 25 W, OUTW W phase output 26 NW Op-amp non inverting input Op-amp output Op-amp inverting input Comparator input NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output) Low-side logic input for U phase Bootstrap voltage for U phase Positive DC input U phase output Negative DC input for W phase page 3/23 STIPNS1M50T-H Internal schematic diagram and pin configuration Figure 2. Pin layout (top view) (*) (*) PIN #1 ID (*) Dummy pin internally connected to P (positive DC input). DS12106 - Rev 3 page 4/23 STIPNS1M50T-H Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings Table 2. Inverter part Symbol VDSS ± ID ± IDP (2) PTOT Parameter Value Unit 500 V Continuous current each MOSFET (TC = 25 °C) 1 A Peak drain current each MOSFET (less than 1 ms) 2 A Total power dissipation for each MOSFET (TC = 25 °C) 10 W MOSFET blocking voltage (or drain-source voltage) for each MOSFET (VIN(1) = 0 V) 1. Applied among HINi, LINi and GND for i = U, V, W. 2. Pulse width limited by max. junction temperature. Table 3. Control part Symbol Parameter Min. Max. Unit Vboot - 21 Vboot + 0.3 V VOUT Output voltage applied among OUTU, OUTV, OUTW - GND VCC Low voltage power supply - 0.3 21 V VCIN Comparator input voltage - 0.3 VCC + 0.3 V Vop+ Op-amp non-inverting input - 0.3 VCC + 0.3 V Vop- Op-amp inverting input - 0.3 VCC + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Logic input voltage applied among HIN, LIN and GND - 0.3 15 V VT/SD/OD Open-drain voltage - 0.3 15 V dVOUT/dt Allowed output slew rate 50 V/ns VIN Table 4. Total system Symbol VISO DS12106 - Rev 3 Parameter Isolation withstand voltage applied between each pin and heat sink plate (AC voltage, t = 60 s) Value Unit 1000 Vrms TJ Power chip operating junction temperature range -40 to 150 °C TC Module case operation temperature range -40 to 125 °C page 5/23 STIPNS1M50T-H Thermal data 2.2 Thermal data Table 5. Thermal data Symbol DS12106 - Rev 3 Parameter Value Unit Rth(j-c) Thermal resistance junction-case single MOSFET 12.5 °C/W Rth(j-a) Thermal resistance junction-ambient (per module) 24 °C/W page 6/23 STIPNS1M50T-H Electrical characteristics 3 Electrical characteristics TJ = 25 °C unless otherwise specified. 3.1 Inverter part Table 6. Static Symbol Parameter Test conditions IDSS Zero-gate voltage drain current V(BR)DSS Drain-source breakdown voltage VCC = Vboot = 15 V, VIN(1) = 0 V, RDS(on) Static drain-source turn-on resistance VCC = Vboot = 15 V, VIN(1) = 0 to 5 V, VSD Drain-source diode forward voltage Min. Typ. VDS = 500 V, VCC = 15 V, VBoot = 15 V ID = 1 mA Max. Unit 1 mA 500 V 3.2 3.6 Ω 0.9 1.6 V Min. Typ. Max. Unit - 226 - ID = 0.5 A VIN(1) = 0 “logic state”, ID = 1 A 1. Applied among HINx, LINx and GND for x=U,V,W. Table 7. Inductive load switching time and energy Symbol ton (1) tc(on) (1) Parameter Test conditions Turn-on time Crossover time (on) VDD = 300 V, - 130 - Turn-off time VCC = Vboot = 15 V, - 248 - Crossover time (off) VIN(2) = 0 to 5 V, - 56 - Reverse recovery time ID = 0.5 A - 155 - Eon Turn-on switching energy (see Figure 4. Switching time definition) - 25 - Eoff Turn-off switching energy - 3.8 - toff (1) tc(off) (1) trr ns µJ 1. tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of MOSFET itself under the internally given gate driving conditions. 2. Applied among HINx, LINx and GND for x=U,V,W. DS12106 - Rev 3 page 7/23 STIPNS1M50T-H Inverter part Figure 3. Switching time test circuit GIPD161120151702RV Figure 4. Switching time definition 100% ID 100% ID t rr ID VDS VIN VIN t ON VIN(ON) VDS ID t C(ON) 10% ID 90% ID 10% VDS t OFF VIN(OFF) (a) turn-on t C(OFF) 10% VDS (b) turn-off 10% ID AM09223V2 Figure 4. Switching time definition refers to HIN, LIN inputs (active high). DS12106 - Rev 3 page 8/23 STIPNS1M50T-H Control part 3.2 Control part (VCC = 15 V unless otherwise specified). Table 8. Low voltage power supply Symbol Min. Typ. Max. Unit VCC UV hysteresis 1.2 1.5 1.8 V VCC_thON VCC UV turn ON threshold 11.5 12 12.5 V VCC_thOFF VCC UV turn OFF threshold 10 10.5 11 V VCC_hys Parameter Test conditions Iqccu Undervoltage quiescent supply current VCC = 15 V, T/SD/OD = 5 V, LIN = 0 V, HIN = 0 V, CIN = 0 V 150 µA Iqcc Quiescent current VCC = 15 V, T/SD/OD = 5 V, LIN = 0 V, HIN = 0 V, CIN = 0 V 1 mA Vref Internal comparator (CIN) reference voltage 0.5 0.54 0.58 V Min. Typ. Max. Unit VBS UV hysteresis 1.2 1.5 1.8 V VBS_thON VBS UV turn-ON threshold 11.1 11.5 12.1 V VBS_thOFF VBS UV turn-OFF threshold 9.8 10 10.6 V IQBSU Undervoltage VBS quiescent current 70 110 µA IQBS VBS quiescent current 200 300 µA Table 9. Bootstrapped voltage Symbol VBS_hys RDS(on) Parameter Bootstrap driver on-resistance Test conditions VBS < 9 V, T/SD/OD = 5 V, LIN = 0 V and HIN = 5 V, CIN = 0 V VBS = 15 V, T/SD/OD = 5 V, LIN = 0 V and HIN = 5 V, CIN = 0 V LVG ON 120 Ω Table 10. Logic inputs Symbol Vil Low logic level voltage Vih High logic level voltage Test conditions Min. Typ. Max. Unit 0.8 V 2.25 IHINh HIN logic “1” input bias current HIN = 15 V IHINI HIN logic “0” input bias current HIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ILINI LIN logic “0” input bias current LIN = 0 V ISDh SD logic “0” input bias current SD = 15 V ISDI SD logic “1” input bias current SD = 0 V Dead time see Figure 9. Dead time and interlocking waveform definitions Dt DS12106 - Rev 3 Parameter 20 20 200 V 40 40 350 180 100 µA 1 µA 100 µA 1 µA 500 µA 3 µA ns page 9/23 STIPNS1M50T-H Control part Table 11. Op-amp characteristics Symbol Parameter Vio Input offset voltage Iio Input offset current Iib Input bias current Test conditions Min. Typ. Max. Unit 6 mV 4 40 nA 100 200 nA 75 150 mV Vic = 0 V, Vo = 7.5 V Vic = 0 V, Vo = 7.5 V (1) VOL Low level output voltage RL = 10 kΩ to VCC VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V Source, Vid = +1 V, Vo = 0 V 16 30 mA Sink, Vid = -1 V, Vo = VCC 50 80 mA Slew rate Vi = 1 - 4 V, CL = 100 pF, unity gain 2.5 3.8 V/µs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB CMRR Common mode rejection ratio 55 70 dB Min. Typ. Io SR Output short-circuit current 1. The direction of input current is out of the IC. Table 12. Sense comparator characteristics Symbol Iib Parameter Test conditions Max. Unit Input bias current VCIN = 1 V 1 µA Vod Open-drain low level output voltage Iod = 3 mA 0.5 V RON_OD Open-drain low level output resistance Iod = 3 mA RPD_SD SD pull-down resistor (1) td_comp Comparator delay T/SD/OD pulled to 5 V through 100 kΩ resistor 90 SR Slew rate CL = 180 pF, Rpu = 5 kΩ 60 tsd Shutdown to high- / low-side driver propagation delay VOUT = 0 V, Vboot = VCC, VIN = 0 to 3.3 V 50 125 200 tisd Comparator triggering to high- / low-side driver turn-off propagation delay Measured applying a voltage step from 0 V to 3.3 V to pin CIN 50 200 250 166 Ω 125 kΩ 130 ns V/µs ns 1. Equivalent values as a result of the resistances of three drivers in parallel. DS12106 - Rev 3 page 10/23 STIPNS1M50T-H Control part Table 13. Truth table Logic input (VI) Condition T/SD/OD Output LIN HIN LVG HVG (1) X(1) L L Shutdown enable half-bridge tri-state L Interlocking half-bridge tri-state H H H L L 0 “logic state” half-bridge tri-state H L L L L 1 “logic state” low-side direct driving H H L H L 1 “logic state” high-side direct driving H L H L H X 1. X: don’t care. 3.2.1 NTC thermistor Figure 5. Internal structure of SD and NTC Vbias R SD LIN VT/SD/OD Vboot SD/OD C SD NTC HVG HIN VCC OUT RPD_SD LVG GND CIN RPD_SD: equivalent value as result of resistances of three drivers in parallel. DS12106 - Rev 3 page 11/23 STIPNS1M50T-H Control part Figure 6. Equivalent resistance (NTC//RPD_SD) 140 Equivalent Resistance (kΩ) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 7. Equivalent resistance (NTC//RPD_SD) zoom 14 12 Equivalent Resistance (kΩ) 10 8 6 4 2 0 70 80 90 100 110 120 Temperature (°C) DS12106 - Rev 3 page 12/23 STIPNS1M50T-H Control part Figure 8. Voltage of T/SD/OD pin according to NTC temperature 5.0 SD/OD: high 4.5 VBias = 5 V R SD = 2.2 kΩ VSD(V) 4.0 3.5 VBias = 3.3 V RSD = 1.0 kΩ 3.0 2.5 2.0 25 50 75 100 125 Temperature (°C) DS12106 - Rev 3 page 13/23 STIPNS1M50T-H Waveform definitions 3.3 Waveform definitions DS12106 - Rev 3 CKIN GG ERO L INT INT ERO L CKIN G Figure 9. Dead time and interlocking waveform definitions page 14/23 STIPNS1M50T-H Shutdown function 4 Shutdown function The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection. The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting input pin (CIN) can be connected to an external shunt resistor for current monitoring. Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs, whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which fixes the disabling time. For an effective design of the shutdown circuit, please refer to Application note AN4966. Figure 10. Shutdown timing waveforms GADG250120171515FSR V REF CI N H IN or LIN U V, W H VG or LVG PROTECT ION SD /OD or T/SD/OD A B open -drain ga te (interna l) A B ∗ ∗ ∗ ∗ ≅ ∗ _ ∗ RSD and CSD external circuitry must be designed to ensure Please refer to AN4966 for further details. * RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin. DS12106 - Rev 3 page 15/23 DS12106 - Rev 3 RS 5V/3.3 V R2 + - Vcc CSD RSD Cvcc R1 R3 HIN W 5V/3.3 V R1 R1 LinU(16 ) C OP OP-(8 ) VccV(9 ) C1 C1 VccW(3 ) HinW(4 ) LinW(5 ) OP+(6 ) OPOUT(7 ) C1 HinV(10 ) C1 LinV(11 ) CSF Cin(12 ) VccU(13 ) C1 HinU(14 ) T/SD/OD(15 ) C1 DZ1 SGN_GND GND(1 ) T/SD/OD(2 ) RSF C2 ADC R5 R4 R1 R1 SD Temp. Monitoring MICROCONTROLLE R LIN W ADC HIN V LIN V R1 HIN U RS R1 NTC GND VCC HIN SD/OD LIN GND OPOUT OP- VCC HIN SD/OD LIN GND VCC HIN SD/OD LIN LVG OUT HVG Vboot OP+ LVG OUT HVG Vboot CIN LVG OUT HVG Vboot CbootU RS (26)N W (25)W,OUT W CbootW (24)Vboot W (23)N V (22)V,OUT V CbootV (21)Vboot V (20)N U (19)U,OUT U (18) P (17)Vboot U C3 C3 C3 DZ2 DZ2 DZ2 PWR _GND Rshunt M C4 VDC Cvdc + - 5 LIN U Application circuit example STIPNS1M50T-H Application circuit example Figure 11. Application circuit example GADG100620160912FSR Application designers are free to use a different scheme according to the specifications of the device. page 16/23 STIPNS1M50T-H Guidelines 5.1 Guidelines • • Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns and placed as close as possible to the IPM input pins. The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible to the Vcc pin and in parallel with the bypass capacitor. • The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin. • The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases, due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold, the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin. • The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires. To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener diode (Dz2) can be placed in parallel with each Cboot. • • The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has priority over Cvdc). • By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals without an opto-couplers is possible. Low-inductance shunt resistors have to be used for phase leg current sensing. In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as possible. The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can reduce the impact of power ground fluctuation. • • • These guidelines ensure the specifications of the device for application designs. For further details, please refer to the relevant application note. Table 14. Recommended operating conditions Symbol Test conditions Min. VPN Supply voltage Applied among P-Nu, Nv, Nw VCC Control supply voltage Applied to VCC-GND VBS High-side bias voltage Applied to VBOOTi-OUTi for i = U, V, W 13 tdead Blanking time to prevent arm-short For each input signal 1 fPWM PWM input signal TC DS12106 - Rev 3 Parameter Case operation temperature -40 °C < TC < 100 °C -40 °C < TJ < 125 °C 13.5 Typ. Max. Unit 300 400 V 15 18 V 18 V µs 25 kHz 100 °C page 17/23 STIPNS1M50T-H Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 NSDIP-26L package information Figure 12. NSDIP-26L package outline 8374968_4 DS12106 - Rev 3 page 18/23 STIPNS1M50T-H NSDIP-26L package information Table 15. NSDIP-26L package mechanical data Dim. mm Min. Typ. A 3.45 A1 0.10 0.25 A2 3.00 3.10 3.20 A3 1.10 1.30 1.50 b 0.47 b1 0.45 b2 0.63 0.67 c 0.47 0.57 c1 0.45 0.50 0.55 D 29.05 29.15 29.25 D1 0.70 D2 0.45 D3 0.90 0.57 0.50 D4 0.55 29.65 E 12.35 12.45 12.55 E1 16.70 17.00 17.30 E2 0.35 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 L 1.24 1.39 1.54 L1 1.00 1.15 1.30 L2 0.25 BSC L3 2.275 REF R1 0.25 0.40 0.55 R2 0.25 0.40 0.55 0.39 0.55 S ϴ 0° ϴ1 ϴ2 DS12106 - Rev 3 Max. 8° 3° BSC 10° 12° 14° page 19/23 STIPNS1M50T-H NSDIP-26L package information Figure 13. NSDIP-26L recommended footprint (dimensions are in mm) 8374968_4_fp DS12106 - Rev 3 page 20/23 STIPNS1M50T-H Revision history Table 16. Document revision history Date Revision 13-Apr-2017 1 Changes Initial release. Datasheet status promoted from preliminary to production data. Updated features on cover page. 08-Jan-2018 2 Updated Table 3: "Inverter part", Table 5: "Total system", Table 6: "Thermal data" and Table 13: "Sense comparator characteristics". Updated Section 6.1: "NSDIP-26L package information". Removed maturity status indication from cover page. Updated Section 2 Electrical ratings. Updated Table 8. Low voltage power supply and Table 10. Logic inputs. 19-Aug-2019 3 Updated Section 4 Shutdown function. Updated Section 5.1 Guidelines. Updated Section 6.1 NSDIP-26L package information. Minor text changes. DS12106 - Rev 3 page 21/23 STIPNS1M50T-H Contents Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 3.3 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5 Application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.1 6 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6.1 NSDIP-26L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DS12106 - Rev 3 page 22/23 STIPNS1M50T-H IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12106 - Rev 3 page 23/23