STK22N6F3
N-channel 60 V, 0.0055 Ω, 22 A, PolarPAK®
STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on) max
STK22N6F3
60 V
< 0.006 Ω
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Description
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■
Ultra low top and bottom junction to case
thermal resistance
■
Extremely low on-resistance RDS(on)
■
Very low switching gate charge
■
Fully encapsulated die
■
100% matte tin finish (in compliance with the
2002/95/EC european directive)
■
High avalanche ruggedness
■
PolarPAK® is a trademark of VISHAY
PolarPAK®
Figure 1.
■
Internal schematic diagram
Switching applications
This STripFET™ III Power MOSFET technology
is among the latest improvements, which have
been especially tailored to minimize on-state
resistance providing superior switching
performances.
Table 1.
Bottom View
Top View
Device summary
Order code
Marking
Package
Packaging
STK22N6F3
2263
PolarPAK®
Tape and reel
April 2009
Doc ID 14850 Rev 2
1/15
www.st.com
15
Contents
STK22N6F3
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
3
Electrical characteristics (curves)
Test circuits
............................. 6
.............................................. 8
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
Doc ID 14850 Rev 2
STK22N6F3
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
60
V
± 20
V
Drain current (continuous) at TC = 25°C
22
A
Drain current (continuous) at TC = 100°C
13.7
A
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID
(1)
ID
IDM
(2)
PTOT
(1)
Drain current (pulsed)
88
Total dissipation at TC = 25°C
5.2
Derating factor
Single pulse avalanche energy
Tj
Tstg
Operating junction temperature
Storage temperature
O
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-
Parameter
Rthj-c
W/°C
mJ
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s
t(
°C
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Max.
Unit
20
24
°C/W
Thermal resistance junction-case (top drain)
0.8
1
°C/W
Thermal resistance junction-case (source)
2.2
2.7
°C/W
du
ro
P
e
Rthj-c
(3)
c
u
d
W
Typ.
Rthj-amb(1) Thermal resistance junction-amb
(2)
P
e
let
o
s
b
3. Starting TJ = 25 °C, ID = 11 A, VDD = 48 V
Symbol
du
-55 to 150
2. Pulse width limited by package
Thermal data
ct
ro
800
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10 sec
Table 3.
A
0.0416
EAS (3)
(s)
)
s
(
ct
1. When mounted on FR-4 board of 1inch2, 2 oz Cu and ≤ 10sec
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2. Steady state
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3. Measured at source pin when the device is mounted on FR-4 board in steady state
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Doc ID 14850 Rev 2
3/15
Electrical characteristics
2
STK22N6F3
Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max.
Unit
60
-
-
V
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,Tc=125 °C
-
-
10
100
µA
µA
IGSS
Gate body leakage current
(VDS = 0)
VGS = ± 20V
-
-
±200
nA
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
2
-
4
V
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 11 A
-
V(BR)DSS
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Table 5.
Symbol
Ω
Dynamic
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25 V, f=1 MHz, VGS=0
-
2500
536
44
-
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD=48 V, ID = 22 A
VGS =10 V
Figure 14
-
41
12
10
-
nC
nC
nC
RG
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
-
0.9
-
Ω
Table 6.
Symbol
4/15
0.0055 0.006
Switching times
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on delay time
Rise time
VDD= 30 V, ID= 11 A,
RG=4.7 Ω, VGS= 10 V
Figure 13
-
16
14
-
ns
ns
td(off)
tf
Turn-off delay time
Fall time
VDD=30 V, ID= 11 A,
RG=4.7 Ω, VGS= 10 V
Figure 13
-
28
5
-
ns
ns
Doc ID 14850 Rev 2
STK22N6F3
Electrical characteristics
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
ISDM(1)
Source-drain current
Source-drain current
(pulsed)
VSD(2)
Forward on voltage
ISD= 22 A, VGS=0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 22 A, di/dt = 100 A/µs,
VDD=30 V, Tj=150°C
Figure 18
ISD
trr
Qrr
IRRM
Min.
Typ.
Max.
Unit
-
-
22
88
A
A
-
-
1.2
V
-
49
91
3.7
-
ns
nC
A
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1. Pulse width limited by package
2.
Pulsed: pulse duration = 300µs, duty cycle 1.5%
Doc ID 14850 Rev 2
5/15
Electrical characteristics
STK22N6F3
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
AM03397v1
ID
(A)
s
ai
are on)
S(
his
n t x RD
i
on ma
i
t
era by
Op ited
Lim
1000
100
10
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10ms
100ms
1s
Tj=150°C
Tc=25°C
1
Sinlge
pulse
0.01
0.1
Figure 4.
ID
(A)
10
1
VDS(V)
Output characteristics
Figure 5.
AM03398v1
VGS=10V
Transfer characteristics
AM03399v1
ID
(A)
7V
200
200
6V
175
175
150
150
125
125
100
100
75
75
50
50
5V
25
0
0
Figure 6.
2
4
6
8 VDS(V)
Normalized BVDSS vs temperaure
AM03400v1
BVDSS
(norm)
1.10
VDS=8V
25
0
0
Figure 7.
2
4
6
8 VGS(V)
Static drain-source on resistance
AM03891v1
RDS(on)
(Ω)
5.8
ID=11A
VGS=10V
5.7
5.6
1.05
5.5
1.00
5.4
5.3
0.95
5.2
0.90
-50 -25
5.0
5.1
6/15
0
25
50
75 100 125 150 TJ(°C)
Doc ID 14850 Rev 2
0
5
10
15
20
ID(A)
STK22N6F3
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM03892v1
VGS
(V)
12
AM03893v1
C
(pF)
6010
VDD=48V
ID=22A
10
Capacitance variations
5010
8
4010
6
3010
4
2010
2
1010
Ciss
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Coss
Crss
0
0
10
5
20
15
25 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM03894v1
VGS(th)
(norm)
10
0
10
20
30
40
50
VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM03895v1
RDS(on)
(norm)
1.1
2.0
1.0
0.9
1.5
0.8
1.0
0.7
0.6
0.5
0.5
0.4
-50
0
50
150 TJ(°C)
100
0
-50 -25
0
25 50
75 100 125 TJ(°C)
Figure 12. Source-drain diode forward
characteristics
AM03896v1
VSD
(V)
TJ=-50°C
0.90
0.80
TJ=25°C
0.70
0.60
0.50
5
TJ=175°C
7
9
11 13 15
17 19 21 ISD(A)
Doc ID 14850 Rev 2
7/15
Test circuits
3
STK22N6F3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
)
s
(
t
VG
2.7kΩ
c
u
d
PW
47kΩ
1kΩ
PW
D.U.T.
o
r
P
AM01468v1
e
t
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d
)
s
t(
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
o
s
b
A
O
)
D
G
L=100µH
S
s
(
t
c
3.3
µF
B
25 Ω
D
u
d
o
G
RG
S
r
P
e
let
so
1000
µF
)
s
(
ct
u
d
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s
b
O
VDD
s
b
O
t
e
l
o
VDD
r
P
e
VD
2200
µF
3.3
µF
VDD
ID
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
b
O
e
t
le
o
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P
L
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/15
0
Doc ID 14850 Rev 2
10%
AM01473v1
STK22N6F3
Test circuits
Figure 19. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
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Qgs1 Qgs2
Qgd
Doc ID 14850 Rev 2
9/15
Package mechanical data
4
STK22N6F3
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
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10/15
Doc ID 14850 Rev 2
STK22N6F3
Package mechanical data
Table 8.
PolarPAK® (option “L”) mechanical data
mm
inch
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.75
0.80
0.85
0.030
0.031
0.033
A1
0.05
0.002
b1
0.48
0.58
0.68
0.019
0.023
0.027
b2
0.41
0.51
0.61
0.016
0.020
0.024
b3
2.19
2.29
2.39
0.086
0.090
0.094
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b4
0.89
1.04
1.19
0.035
0.041
0.047
b5
0.23
0.33
0.43
0.009
0.013
0.017
c
0.20
0.25
0.30
0.008
0.010
0.012
D
6
6.15
6.30
0.236
0.242
0.248
D1
5.74
5.89
6.04
0.226
0.232
0.238
E
5.01
5.16
5.31
0.197
0.203
0.209
E1
4.75
4.90
5.05
0.187
0.193
0.199
H1
0.23
H2
0.45
H3
0.31
H4
0.45
K1
4.22
K2
1.08
K3
1.37
0.054
K4
0.24
0.009
M1
4.30
4.50
4.70
M2
3.43
3.58
3.73
M3
0.22
0.009
M4
0.05
0.002
P1
0.15
0.20
0.25
T1
3.48
3.64
T2
0.56
0.76
T3
1.20
0.047
T4
3.90
0.154
T5
<
0°
0.009
0.56
0.018
0.51
0.012
0.56
0.018
4.37
4.52
0.166
0.172
0.178
1.13
1.18
0.043
0.044
0.046
0.169
0.177
0.185
0.135
0.141
0.147
0.006
0.008
0.010
4.10
0.137
0.143
0.161
0.95
0.022
0.030
0.037
0.007
0.014
10°
12°
0.41
0.18
0.36
10°
12°
Doc ID 14850 Rev 2
0°
0.022
0.016
0.020
0.022
11/15
Package mechanical data
STK22N6F3
Figure 20. PolarPAK® (option “L”) drawings
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12/15
Doc ID 14850 Rev 2
STK22N6F3
Package mechanical data
Figure 21. Recommended PAD layout
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Doc ID 14850 Rev 2
13/15
Revision history
5
STK22N6F3
Revision history
Table 9.
Document revision history
Date
Revision
Changes
01-Jul-2008
1
First release
16-Apr-2009
2
Document status promoted from preliminary data to datasheet
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14/15
Doc ID 14850 Rev 2
STK22N6F3
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Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
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