STL100N8F7

STL100N8F7 Datasheet N-channel 80 V, 5.2 mΩ typ., 100 A, STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Features PowerFLAT 5x6 D(5, 6, 7, 8) 8 7 6 5 Order code V DS RDS(on) max ID PTOT STL100N8F7 80 V 6.1 mΩ 100 A 120 W • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. NG4D5678S123 Product status link STL100N8F7 Product summary Order code STL100N8F7 Marking 100N8F7 Package PowerFLAT 5x6 Packing Tape and reel DS10666 - Rev 4 - November 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL100N8F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 80 V VGS Gate-source voltage ±20 V ID (1) Drain current (continuous) at Tc= 25 °C 100 A Drain current (continuous) at TC = 100 °C 71 A Drain current (pulsed) 400 A Drain current (continuous) at Tpcb = 25 °C 20 A Drain current (continuous) at Tpcb = 100 °C 14 A Drain current (pulsed) 80 A Total power dissipation at TC = 25 °C 120 W Total power dissipation at Tpcb = 25 °C 4.8 W Single pulse avalanche energy 220 mJ ID (1) IDM (2) (1) ID (3) ID (3) IDM (3) (2) PTOT (1) PTOT (3) EAS (4) TJ Operating junction temperature range Tstg Storage temperature range -55 to 175 °C °C 1. This value is rated according to Rthj-c. 2. Pulse width limited by safe operating area. 3. This value is rated according to Rthj-pcb. 4. Starting TJ=25 °C, ID=25 A, VDD=40 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Value Unit Thermal resistance junction-case 1.25 °C/W Thermal resistance junction-pcb 31.3 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s. DS10666 - Rev 4 page 2/18 STL100N8F7 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0, ID = 250 µA Min. Typ. 80 Zero gate voltage drain current 1 µA 10 µA ±100 nA 4.5 V 5.2 6.1 mΩ Min. Typ. Max. Unit - 3435 - pF - 653 - pF - 57 - pF VGS = 0, VDS = 80 V, TC = 125 °C (1) IGSS Gate-body leakage current VDS = 0, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A Unit V VGS = 0, VDS = 80 V IDSS Max. 2.5 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 40 V, ID = 20 A, - 46.8 - nC Qgs Gate-source charge VGS = 0 to 10 V - 23.4 - nC Qgd Gate-drain charge (see Figure 13. Test circuit for gate charge behavior - 11.2 - nC Test conditions Min. Typ. Max. Unit VDD = 40 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V - 49 - ns - 95 - ns - 60 - ns - 32 - ns VGS = 0, VDS = 40 V, f = 1 MHz Table 5. Switching times Symbol td(on) tr td(off) tf DS10666 - Rev 4 Parameter Turn-on delay time Rise time Turn-off delay time Fall time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform page 3/18 STL100N8F7 Electrical characteristics Table 6. Source-drain diode Symbol VSD (1) Parameter Test conditions Min. Typ. Max. Unit 1.2 V Forward on voltage VGS = 0, ISD = 20 A - trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 48.6 ns Qrr Reverse recovery charge - 58.6 nC IRRM Reverse recovery current VDD = 60 V (see Figure 14. Test circuit for inductive load switching and diode recovery times. - 2.4 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS10666 - Rev 4 page 4/18 STL100N8F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) K GIPG031120151240SOA GIPG281020150856ZTH limited 10 -1 10 2 0.05 t p =10 µs t p =100 µs 10 1 t p =1 ms 10 -2 10 -3 175 t p =10 ms 10 0 10 -1 10 0 V DS (V) 10 1 10 -4 10 -5 V GS = 6 VV GS =5 VV GS =V GS = Figure 3. Output characteristics ID (A) 200 V GS =10 V V GS =9 V 10 -1 10 0 t p (s) GIPG281020150851TCH V DS = 3 V 200 V GS =7 V 160 120 120 V GS =6 V 80 40 80 40 V GS =5 V 0.5 1 1.5 2 2.5 3 3.5 V DS (V) Figure 5. Gate charge vs gate-source voltage V GS (V) 12 10 -2 ID (A) 240 V GS =8 V 160 0 0 10 -3 Figure 4. Transfer characteristics GIPG281020150919OCH 240 10 -4 GIPG281020150856QVG V DD =40 V I D = 20 A 0 2 3 4 5 6 7 8 9 V GS (V) Figure 6. Static drain-source on-resistance R DS(on) (mΩ) GIPD281020150943RID V GS = 10 V 5.4 10 5.3 8 6 5.2 4 5.1 2 0 0 DS10666 - Rev 4 20 40 Q g (nC) 5.0 0 4 8 12 16 20 I D (A) page 5/18 STL100N8F7 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG281020150854CVR V GS(th) (norm.) GIPG281020150910VTH I D = 250 µA 1.1 10 4 C ISS 1.0 10 3 0.9 C OSS 10 2 0.8 f = 1 MHz 0.7 C RSS 10 10 -1 1 10 0 0.6 -75 V DS (V) 10 1 75 V (BR)DSS (norm.) GIPG281020150910RON V GS = 10 V I D = 10 A 2.0 25 125 175 T j (°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) -25 GIPG281020150944BDV I D = 1 mA 1.05 1.8 1.03 1.6 1.4 1.01 1.2 0.99 1.0 0.97 0.8 0.6 -75 -25 25 75 125 175 0.95 -75 T j (°C) -25 25 75 125 175 T j (°C) Figure 11. Source-drain diode forward characteristics V SD (V) GIPG281020150913SDF 1.0 T j = -55 °C 0.9 0.8 T j = 25 °C 0.7 T j = 175 °C 0.6 0.5 0.4 0 DS10666 - Rev 4 4 8 12 16 20 I SD (A) page 6/18 STL100N8F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10666 - Rev 4 page 7/18 STL100N8F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS10666 - Rev 4 page 8/18 STL100N8F7 PowerFLAT 5x6 type C SUBCON package information 4.1 PowerFLAT 5x6 type C SUBCON package information Figure 18. PowerFLAT 5x6 type C SUBCON package outline 8472137_SUBCON_998G_REV4 8472137_SUBCON_998G_REV4 DS10666 - Rev 4 page 9/18 STL100N8F7 PowerFLAT 5x6 type C SUBCON package information Table 7. PowerFLAT 5x6 type C SUBCON package mechanical data Dim. A mm Min. Typ. Max. 0.90 0.95 1.00 A1 b 0.02 0.35 b1 c 0.40 0.30 0.21 0.25 D 0.34 5.10 D1 4.80 4.90 5.00 D2 4.01 4.21 4.31 e 1.17 1.27 1.37 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.54 3.64 3.74 E4 0.15 0.25 0.35 E5 0.26 0.36 0.46 H 0.51 0.61 0.71 K 0.95 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 L2 DS10666 - Rev 4 0.45 0.10 P 1.00 1.10 1.20 θ 8° 10° 12° page 10/18 STL100N8F7 PowerFLAT 5x6 type C package information 4.2 PowerFLAT 5x6 type C package information Figure 19. PowerFLAT 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_Rev18 DS10666 - Rev 4 page 11/18 STL100N8F7 PowerFLAT 5x6 type C package information Table 8. PowerFLAT 5x6 type C package mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS10666 - Rev 4 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 12/18 STL100N8F7 PowerFLAT 5x6 type C package information Figure 20. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_18 DS10666 - Rev 4 page 13/18 STL100N8F7 PowerFLAT 5x6 packing information 4.3 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS10666 - Rev 4 page 14/18 STL100N8F7 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS10666 - Rev 4 page 15/18 STL100N8F7 Revision history Table 9. Document revision history Date Revision 21-Oct-2014 1 Changes Initial release. Modified: Table 2: "Absolute maximum ratings" , Table 5: "Dynamic", Table 6: "Switching times" and Table 7: "Source drain diode". 03-Nov-2015 2 Added: Section 4.1: "Electrical characteristics (curves)". Minor text changes 03-Dec-2015 3 27-Nov-2019 4 Document status promoted from preliminary to production data. Added Section 4.1 PowerFLAT 5x6 type C SUBCON package information. Updated Section 4.2 PowerFLAT 5x6 type C package information. Minor text changes. DS10666 - Rev 4 page 16/18 STL100N8F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 type C SUBCON package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 type C package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 PowerFLAT™ 5x6 type C packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 DS10666 - Rev 4 page 17/18 STL100N8F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS10666 - Rev 4 page 18/18