STL10N60M6

STL10N60M6 Datasheet N-channel 600 V, 550 mΩ typ., 5.5 A, MDmesh™ M6 Power MOSFET in a PowerFLAT™ 5x6 HV package Features 1 2 3 4 PowerFLAT™ 5x6 HV D(5, 6, 7, 8) Order code VDS RDS(on) max. ID PTOT STL10N60M6 600 V 660 mΩ 5.5 A 48 W • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • G(4) Switching applications LLC converters Boost PFC converters Description S(1, 2, 3) AM15540v7 The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STL10N60M6 Product summary Order code STL10N60M6 Marking 10N60M6 Package PowerFLAT™ 5x6 HV Packing Tape and reel DS12876 - Rev 1 - December 2018 For further information contact your local STMicroelectronics sales office. www.st.com STL10N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 5.5 Drain current (continuous) at Tcase = 100 °C 3.5 IDM(1) Drain current (pulsed) 16 A PTOT Total power dissipation at Tcase = 25 °C 48 W IAR(2) Avalanche current, repetitive or not repetitive 1.4 A EAS(3) Single pulse avalanche energy 120 mJ dv/dt(4) Peak diode recovery voltage slope 15 dv/dt(5) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID Tj Parameter Operating junction temperature range A V/ns -55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. Pulse width limited by Tjmax. 3. Starting Tj = 25 °C, ID = IAR, VDD = 50 V. 4. ISD ≤ 5.5 A, di/dt = 400 A/μs, VDS peak < V(BR)DSS, VDD = 400 V 5. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.6 Rthj-pcb(1) Thermal resistance junction-pcb 50 °C/W 1. When mounted on an 1-inch² FR-4, 2 Oz copper board. DS12876 - Rev 1 page 2/15 STL10N60M6 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 3. Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 IDSS Zero gate voltage drain current VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) 100 IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 4.75 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2.75 A 550 660 mΩ Min. Typ. Max. Unit - 338 - - 26.2 - - 3.8 - 3.25 µA 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 59 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge VDD = 480 V, ID = 6.4 A, - 8.8 - Qgs Gate-source charge VGS = 0 to 10 V - 4.8 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 2.7 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 5. Switching times Symbol td(on) tr td(off) tf DS12876 - Rev 1 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 3.2 A, - 11 - Rise time RG = 4.7 Ω, VGS = 10 V - 8.2 - Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 23 - - 10 - Fall time Unit ns page 3/15 STL10N60M6 Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 5.5 A Source-drain current (pulsed) - 16 A 1.6 V Forward on voltage VGS = 0 V, ISD = 5.5 A - trr Reverse recovery time ISD = 6.4 A, di/dt = 100 A/µs, - 155 ns Qrr Reverse recovery charge VDD = 60 V - 0.813 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 10.5 A trr Reverse recovery time ISD = 6.4 A, di/dt = 100 A/µs, - 250 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 1.35 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 10.8 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12876 - Rev 1 page 4/15 STL10N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG171220181557SOA K ZthPowerFlat_5x6_19 d=0.5 0.2 10 1 tp =1 μs Operation in this area is limited by RDS(on) 10-1 0.1 0.05 0.02 0.01 tp =10 µs tp =100 µs 10-2 10 0 Single pulse tp =1 ms Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V tp =10 ms 10 -1 10 -1 10 0 10 1 VDS (V) 10 2 10-3 -6 10 Figure 3. Output characteristics ID (A) 10-3 10-2 10-1 100 tp(s) Figure 4. Transfer characteristics ID (A) GADG171220181557OCH VGS = 10 V 16 10-5 10-4 GADG171220181557TCH 16 VGS = 9 V 12 12 VGS = 8 V 8 VDS = 16 V 8 VGS = 7 V 4 4 VGS = 6 V 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VDS (V) GADG171220181558QVG VDD = 480 V, ID = 6.4 A 600 12 Qg 500 400 VGS (V) 10 Qgd Qgs 0 4 5 8 9 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (mΩ) GADG171220181559RID 610 590 VGS = 10 V 570 6 200 4 VDS 100 DS12876 - Rev 1 7 8 300 0 0 6 2 2 4 6 8 10 0 Qg (nC) 550 530 510 0 1 2 3 4 5 ID (A) page 5/15 STL10N60M6 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) GADG171220181558CVR GADG171220181558EOS 3.0 10 3 2.5 CISS 2.0 10 2 1.5 10 1 10 0 10 -1 f = 1 MHz 10 0 10 1 10 2 COSS 1.0 CRSS 0.5 VDS (V) Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GADG171220181600VTH 200 300 400 500 600 VDS (V) Figure 10. Normalized on-resistance vs temperature RDS(on) (norm.) GADG171220181600RON 2.0 1.0 VGS = 10 V 1.5 ID = 250 µA 1.0 0.8 0.5 0.7 0.6 -75 100 2.5 1.1 0.9 0 0 -25 25 75 125 Tj (°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG171220181559BDV 0 -75 -25 25 75 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG171220181558SDF 1.1 1.10 125 TJ = -50 °C 1.0 1.05 0.9 TJ = 25 °C ID = 1 mA 1.00 0.8 TJ = 150 °C 0.95 0.7 0.90 0.85 -75 DS12876 - Rev 1 0.6 -25 25 75 125 Tj (°C) 0.5 0 1 2 3 4 5 ISD (A) page 6/15 STL10N60M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD IG= CONST VGS RG 1 kΩ 100 nF RL VGS 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12876 - Rev 1 page 7/15 STL10N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12876 - Rev 1 page 8/15 STL10N60M6 PowerFLAT™ 5x6 HV package information 4.1 PowerFLAT™ 5x6 HV package information Figure 19. PowerFLAT™ 5x6 HV package outline 8368143_Rev_4 DS12876 - Rev 1 page 9/15 STL10N60M6 PowerFLAT™ 5x6 HV package information Table 7. PowerFLAT™ 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS12876 - Rev 1 page 10/15 STL10N60M6 PowerFLAT™ 5x6 packing information 4.2 PowerFLAT™ 5x6 packing information Figure 21. PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification DS12876 - Rev 1 page 11/15 STL10N60M6 PowerFLAT™ 5x6 packing information Figure 23. PowerFLAT™ 5x6 reel DS12876 - Rev 1 page 12/15 STL10N60M6 Revision history Table 8. Document revision history DS12876 - Rev 1 Date Version 18-Dec-2018 1 Changes First release. page 13/15 STL10N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT™ 5x6 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT™ 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12876 - Rev 1 page 14/15 STL10N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12876 - Rev 1 page 15/15