STL11N3LLH6

STL11N3LLH6 N-channel 30 V, 6 mΩ typ., 11 A STripFET™ H6 Power MOSFET in a PowerFLAT™ 3.3x3.3 package Datasheet - production data Features     Order code VDS RDS(on) max ID STL11N3LLH6 30 V 7.5 mΩ 11 A Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Switching applications Description Figure 1: Internal schematic diagram D(5, 6, 7, 8) 8 7 6 5 1 2 3 4 This device is an N-channel Power MOSFET developed using the STripFET™ H6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. G(4) S(1, 2, 3) AM15810v1 Table 1: Device summary Order code Marking Package Packing STL11N3LLH6 11N3L PowerFLATTM 3.3x3.3 Tape and reel February 2017 DocID17755 Rev 3 This is information on a product in full production. 1/14 www.st.com Contents STL11N3LLH6 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/14 PowerFLAT™ 3.3x3.3 package information .................................... 10 Revision history ............................................................................ 13 DocID17755 Rev 3 STL11N3LLH6 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at Tpcb = 25 °C 11 A ID(1) Drain current (continuous) at Tpcb = 100 °C 6.9 A IDM(2) Drain current (pulsed) 44 A PTOT (1) Total dissipation at Tpcb = 25 °C 2.9 W PTOT (3) Total dissipation at TC = 25 °C 45 W -55 to 150 °C Value Unit Thermal resistance junction-case 2.8 °C/W Thermal resistance junction-pcb 42.8 °C/W Value Unit 90 mJ Tj Operating junction temperature range Tstg Storage temperature range Notes: (1)This value is rated according to Rthj-pcb. (2)Pulse (3)The width limited by safe operating area. value is rated according to Rthj-c. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s Table 4: Avalanche characteristics Symbol EAS Parameter Single pulse avalanche energy (starting TJ = 25 °C, ID = 5.5 A, L = 6 mH) DocID17755 Rev 3 3/14 Electrical characteristics 2 STL11N3LLH6 Electrical characteristics (TC = 25 °C unless otherwise specified). Table 5: On /off states Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Test conditions Drain-source breakdown voltage ID = 250 μA, VGS = 0 V Min. Typ. Max. Unit V 30 VGS = 0 V, VDS = 30 V 1 µA VGS = 0 V, VDS = 30 V, TC = 125 °C(1) 10 µA Gate-body leakage current VGS = ±20 V, VDS = 0 V ±100 nA Gate threshold voltage VDS = VGS, ID = 250 μA Static drain-source on-resistance VGS = 10 V, ID = 5.5 A 6 7.5 mΩ VGS = 4.5 V, ID = 5.5 A 8.4 9.5 mΩ Min. Typ. Max. Unit - 1690 - pF - 290 - pF - 176 - pF - 17 - nC - 8 - nC - 7 - nC - 1.7 - Ω Zero gate voltage drain current 1 V Notes: (1)Defined by design, not subject to production test Table 6: Dynamic Symbol Ciss 4/14 Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS= 0 V Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge RG Gate input resistance charge VDD = 15 V, ID = 11 A, VGS = 0 to 4.5 V (see Figure 14: "Test circuit for gate charge behavior") f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV open drain DocID17755 Rev 3 STL11N3LLH6 Electrical characteristics Table 7: Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time Min. Typ. Max. Unit - 9.5 - ns - 30 - ns - 37 - ns - 12 - ns Min. Typ. VDD = 15 V, ID = 5.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" Rise time Turn-off delay time Fall time Table 8: Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 11 A, VGS = 0 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ID = 11 A, di/dt = 100 A/µs, VDD = 24 V - Max. Unit 1.1 V - 24 ns - 16.8 nC - 1.4 A Notes: (1)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID17755 Rev 3 5/14 Electrical characteristics 2.1 STL11N3LLH6 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized V(BR)DSS vs temperature Figure 7: Static drain-source on-resistance 6/14 DocID17755 Rev 3 STL11N3LLH6 Electrical characteristics Figure 8: Gate charge vs gate-source voltage Figure 9: Capacitance variations Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics DocID17755 Rev 3 7/14 Test circuits 3 8/14 STL11N3LLH6 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID17755 Rev 3 STL11N3LLH6 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID17755 Rev 3 9/14 Package information 4.1 STL11N3LLH6 PowerFLAT™ 3.3x3.3 package information Figure 19: PowerFLAT™ 3.3x3.3 package outline BOTTOM VIEW SIDE VIEW TOP VIEW 8465286_ A 10/14 DocID17755 Rev 3 STL11N3LLH6 Package information Table 9: PowerFLAT™ 3.3x3.3 package mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 030 0.45 0.60 L1 0.05 0.15 0.25 L2 θ 0.15 8° DocID17755 Rev 3 10° 12° 11/14 Package information STL11N3LLH6 Figure 20: PowerFLAT™ 3.3x3.3 recommended footprint 8465286_footprint 12/14 DocID17755 Rev 3 STL11N3LLH6 5 Revision history Revision history Table 10: Document revision history Date Revision 04-Jan-2017 1 First release 11-Jan-2017 2 Updated information on cover page. 3 Updated title, features and description on cover page. Updated Section 1: "Electrical ratings". Updated Section 2: "Electrical characteristics". Minor text changes 20-Feb-2017 Changes DocID17755 Rev 3 13/14 STL11N3LLH6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 14/14 DocID17755 Rev 3