STL11N4LLF5

STL11N4LLF5 N-channel 40 V, 9.1 mΩ typ., 15 A STripFET™V Power MOSFET in a PowerFLAT™ 3.3 x 3.3 package Datasheet − production data Features Order code VDS RDS(on) max ID STL11N4LLF5 40 V 9.7 mΩ 15 A ■ Low gate charge ■ Very low on-resistance ■ High avalance ruggedeness PowerFLAT™ 3.3x3.3 Applications ■ Switching applications Description Figure 1. Internal schematic diagram This device is an N-channel Power MOSFET developed using STMicroelectronics’ STripFET™V technology. The device has been optimized to achieve very low on-state resistance, contributing to a FOM that is among the best in its class. Table 1. Device summary Order code Marking Package Packaging STL11N4LLF5 11N4LLF5 PowerFLAT™ 3.3 x 3.3 Tape and reel February 2013 This is information on a product in full production. Doc ID 024286 Rev 1 1/14 www.st.com 14 Contents STL11N4LLF5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 .............................................. 8 Doc ID 024286 Rev 1 STL11N4LLF5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ± 20 V ID(1) Drain current (continuous) at Tpcb = 25 °C 11 A ID (1) Drain current (continuous) at Tpcb=100 °C 6.8 A IDM(2) Drain current (pulsed) 44 A PTOT (3) Total dissipation at TC = 25 °C 50 W PTOT (1) Total dissipation at Tpcb = 25 °C 2.9 W Derating factor (3) 0.4 W/°C -55 to 150 °C Value Unit TJ Operating junction temperature storage temperature Tstg 1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. 3. The vaule is rated according Rthj-c Table 3. Thermal resistance Symbol Parameter Rthj-case Thermal resistance junction-case 2.5 °C/W (1) Thermal resistance junction-pcb 42.8 °C/W Rthj-pcb (2) Thermal resistance junction-pcb 63.5 °C/W Rthj-pcb 1. When mounted on FR-4 board of 1inch² , 2oz Cu, t < 10sec 2. Steady state Doc ID 024286 Rev 1 3/14 Electrical characteristics 2 STL11N4LLF5 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS Parameter Test conditions Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) ID = 250 μA, VGS= 0 VGS(th) Gate threshold voltage VDS= VGS, ID = 250 μA Static drain-source onresistance VGS= 10 V, ID= 5.5 A RDS(on) Symbol Ciss Coss Crss Qg Parameter Input capacitance Output capacitance Reverse transfer capacitance tr td(off) tf Min. VDD=15 V, ID = 11 A Gate input resistance td(on) Unit V 1 10 μA μA ±100 μA 2.5 V 9.1 10.6 9.7 12 mΩ mΩ Typ. Max. Unit 1 VDS =25 V, f=1 MHz, VGS=0 RG Symbol 40 VGS= 4.5 V, ID= 5.5 A Test conditions Qgd Table 6. Max. Dynamic Total gate charge Gate-source charge Gate-drain charge Qgs Typ. VDS = 40 V, TC=125 °C VGS = ± 20 V Table 5. Min. VDS = 40 V, Gate body leakage current (VDS = 0) IGSS 4/14 On/off states VGS =4.5 V (see Figure 14) 1570 257 32 pF pF pF 12.9 3.9 5.3 nC nC nC f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV ID=0 0.5 1.5 2.5 Test conditions Min. Typ. Max. Unit - 14 42 37 5.2 - ns ns ns ns Ω Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time VDD=15 V, ID= 5.5 A, RG=4.7 Ω, VGS=4.5 V (see Figure 13) Doc ID 024286 Rev 1 STL11N4LLF5 Electrical characteristics Table 7. Symbol ISD Source drain diode Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 11 A ISDM(1) Source-drain current (pulsed) - 44 A VSD(2) Forward on voltage - 1.1 V trr Qrr IRRM ISD=11 A, VGS=0 ISD=11 A, Reverse recovery time Reverse recovery charge Reverse recovery current di/dt = 100 A/μs, VDD=20 V, Tj=150 °C - 27.2 24.5 1.8 ns nC A (see Figure 18) 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration=300 μs, duty cycle 1.5% Doc ID 024286 Rev 1 5/14 Electrical characteristics STL11N4LLF5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. $0Y AM15489v1 K δ=0.5 RQ  2 S /L HUD P LWH WLRQ GĆ ĆLQ E\ ĆW ĆP KLV D[ ĆD Ć5 UH DĆ ' 6 LV ,' $ Thermal impedance -1 10 0.05 0.02 0.01  PV 10 -2 Single pulse    Figure 4. ,' $ 10 -3 7M ƒ& 7F ƒ& PV 6LQJOH SXOVH V   9'69 Output characteristics 10 -4 10 -4 10 -3 Figure 5. $0Y 9*6 9 10 -2 10 -1 1 tp(s) 10 Transfer characteristics $0Y ,' $ 9'6 Ć9   9   9   9    Figure 6.     9'69 Normalized BVDSS vs temperature $0Y %9'66 QRUP    Figure 7.     9*69 Static drain-source on-resistance $0Y 5'6RQ 2KP ,' —$         6/14     7-ƒ&   Doc ID 024286 Rev 1 9*6 9    ,'$ STL11N4LLF5 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. $0Y 9*6 9 9'' 9 ,' $  Capacitance variations $0Y & S)    &LVV         &RVV       4JQ& Figure 10. Normalized gate threshold voltage vs temperature $0Y 9*6WK QRUP   &UVV     9'69 Figure 11. Normalized on-resistance vs temperature $0Y 5'6RQ QRUP                  7-ƒ&       7-ƒ& Figure 12. Source-drain diode forward characteristics $0Y 96' 9 7- ƒ&  7- ƒ&  7- ƒ&        ,6'$ Doc ID 024286 Rev 1 7/14 Test circuits 3 STL11N4LLF5 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 17. Unclamped inductive waveform AM01471v1 Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/14 0 Doc ID 024286 Rev 1 10% AM01473v1 STL11N4LLF5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 024286 Rev 1 9/14 Package mechanical data Table 8. STL11N4LLF5 PowerFLAT™ 3.3 x 3.3 mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.05 A3 0.20 b 0.23 D 3.20 D2 2.50 E 3.20 E2 1.25 e L 10/14 0.38 3.30 3.40 2.75 3.30 3.40 1.50 0.65 0.30 Doc ID 024286 Rev 1 0.50 STL11N4LLF5 Package mechanical data Figure 19. PowerFLAT™ 3.3 x 3.3 drawing 7635509_G Doc ID 024286 Rev 1 11/14 Package mechanical data STL11N4LLF5 0.41 Figure 20. PowerFLAT™ 3.3 x 3.3 recommended footprint 0.65 0.55 0.67 1.47 3.35 0.66 2.75 0.40 0.31 7635509_G_footprint 12/14 Doc ID 024286 Rev 1 STL11N4LLF5 5 Revision history Revision history Table 9. Document revision history Date Revision 19-Feb-2013 1 Changes First release Doc ID 024286 Rev 1 13/14 STL11N4LLF5 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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