STL11N6F7
N-channel 60 V, 10 mΩ typ., 11 A STripFET™ F7
Power MOSFET in a PowerFLAT™ 3.3x3.3 package
Datasheet - production data
Features
1
2
3
Order code
VDS
RDS(on) max.
ID
STL11N6F7
60 V
12 mΩ
11 A
Features
4
PowerFLAT™ 3.3x3.3
Applications
Figure 1: Internal schematic diagram
D(5, 6, 7, 8)
8
7
6
Among the lowest RDS(on) on the market
Excellent figure of merit (FoM)
Low Crss/Ciss ratio for EMI immunity
High avalanche ruggedness
5
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low onstate resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
G(4)
S(1, 2, 3)
1
2
3
4
AM15810v1
Table 1: Device summary
Order code
Marking
Package
Packing
STL11N6F7
11N6F
PowerFLAT™ 3.3x3.3
Tape and reel
November 2015
DocID028134 Rev 2
This is information on a product in full production.
1/13
www.st.com
Contents
STL11N6F7
Contents
1
Electrical ratings ............................................................................... 3
2
Electrical characteristics ................................................................. 4
2.1
Electrical characteristics (curve)........................................................ 5
3
Test circuits ...................................................................................... 7
4
Package mechanical data ................................................................ 8
4.1
5
2/13
PowerFLAT 3.3x3.3 package information ......................................... 9
Revision history .............................................................................. 12
DocID028134 Rev 2
STL11N6F7
1
Electrical ratings
Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
60
V
VGS
Gate source voltage
±20
V
Drain current (continuous) at TC = 25 °C
47
Drain current (continuous) at TC = 100 °C
30
Drain current (pulsed)
188
Drain current (continuous) at Tpcb = 25 °C
11
Drain current (continuous) at Tpcb = 100 °C
7
ID(1)
IDM(1)(2)
ID(3)
IDM(2)(3)
A
A
A
Drain current (pulsed)
44
A
PTOT
(1)
Total dissipation at TC = 25 °C
48
W
PTOT
(3)
Total dissipation at Tpcb = 25 °C
2.9
W
-55 to 150
°C
TJ
Operating junction temperature
Tstg
Storage temperature
Notes:
(1)
This value is rated according to Rthj-c
(2)
Pulse width limited by safe operating area
(3)
This value is rated according to Rthj-pcb
Table 3: Thermal data
Symbol
Rthj-pcb
(1)
Rthj-case
Parameter
Value
Unit
Thermal resistance junction-pcb max
42.8
°C/W
Thermal resistance junction-case max
2.6
°C/W
Notes:
(1)
When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec
DocID028134 Rev 2
3/13
Electrical characteristics
2
STL11N6F7
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: Static
Symbol
V(BR)DSS
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
Drain-source breakdown voltage
ID= 1mA, VGS = 0 V
60
IDSS
Zero gate voltage drain current
VGS= 0 V , VDS=60 V
1
µA
IGSS
Gate-body leakage current
VGS = 20 V, VDS = 0 V
100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 μA
4
V
RDS(on)
Static drain-source on-resistance
VGS = 10 V, ID = 5.5 A
10
12
mΩ
Min.
Typ.
Max.
Unit
2
Table 5: Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
-
1035
-
pF
Coss
Output capacitance
-
450
-
pF
Crss
Reverse transfer
capacitance
-
53
-
pF
Qg
Total gate charge
-
17
-
nC
Qgs
Gate-source charge
-
5.7
-
nC
Qgd
Gate-drain charge
-
5.7
-
nC
Min.
Typ.
Max.
Unit
-
14.5
-
ns
-
15.3
-
ns
-
19.4
-
ns
-
8
-
ns
Min.
Typ.
Max.
Unit
1.2
V
VDS = 30 V, f = 1 MHz,VGS = 0 V
VDD = 30 V, ID = 11 A,
VGS = 10 V
(see Figure 14: "Test circuit for gate
charge behavior")
Table 6: Switching times
Symbol
td(on)
tr
td(off)
tf
Parameter
Turn-on delay
time
Rise time
Turn-off delay
time
Test conditions
VDD = 30 V, ID = 5.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13: "Test circuit for resistive
load switching times")
Fall time
Table 7: Source-drain diode
Symbol
VSD(1)
Parameter
Forward on
voltage
trr
Reverse
recovery time
Qrr
Reverse
recovery charge
IRRM
Reverse
recovery current
Test conditions
ISD = 11 A, VGS = 0 V
-
ID = 11 A, di/dt = 100 A/µs
VDD = 48 V
(see Figure 15: "Test circuit for inductive
load switching and diode recovery
times")
-
26.8
ns
-
14.2
nC
-
1.06
A
Notes:
4/13
DocID028134 Rev 2
STL11N6F7
Electrical characteristics
(1)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2.1
Electrical characteristics (curve)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
DocID028134 Rev 2
5/13
Electrical characteristics
STL11N6F7
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs
temperature
Figure 12: Source-drain diode forward characteristics
6/13
DocID028134 Rev 2
STL11N6F7
3
Test circuits
Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
DocID028134 Rev 2
7/13
Package information
4
STL11N6F7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8/13
DocID028134 Rev 2
STL11N6F7
4.1
Package information
PowerFLAT 3.3x3.3 package information
Figure 19: PowerFLAT™ 3.3x3.3 package outline
BOTTOM VIEW
SIDE VIEW
TOP VIEW
8465286_ A
DocID028134 Rev 2
9/13
Package information
STL11N6F7
Table 8: PowerFLAT™ 3.3x3.3 package mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.70
0.80
0.90
b
0.25
0.30
0.39
c
0.14
0.15
0.20
D
3.10
3.30
3.50
D1
3.05
3.15
3.25
D2
2.15
2.25
2.35
e
0.55
0.65
0.75
E
3.10
3.30
3.50
E1
2.90
3.00
3.10
E2
1.60
1.70
1.80
H
0.25
0.40
0.55
K
0.65
0.75
0.85
L
030
0.45
0.60
L1
0.05
0.15
0.25
L2
θ
10/13
0.15
8°
DocID028134 Rev 2
10°
12°
STL11N6F7
Package information
Figure 20: PowerFLAT™ 3.3x3.3 recommended footprint
8465286_footprint
DocID028134 Rev 2
11/13
Revision history
5
STL11N6F7
Revision history
Table 9: Document revision history
Date
Revisi
on
21-Jul-2015
1
First release.
2
Document status changed from preliminary to production data.
Updated title and features in cover page
Updated Table 2: "Absolute maximum ratings" and Section 4: "Electrical
characteristics".
Added Section 4.1: "Electrical characteristics (curve)".
Minor text changes
17-Nov-2015
12/13
Changes
DocID028134 Rev 2
STL11N6F7
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© 2015 STMicroelectronics – All rights reserved
DocID028134 Rev 2
13/13
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