STL120N8F7

STL120N8F7 Datasheet N-channel 80 V, 4.0 mΩ typ., 120 A STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Features PowerFLAT 5x6 D(5, 6, 7, 8) 8 7 5 6 Order code VDS RDS(on) max. ID PTOT STL120N8F7 80 V 4.8 mΩ 120 A 140 W • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. AM15540v2 Product status link STL120N8F7 Product summary Order code STL120N8F7 Marking 120N8F7 Package PowerFLAT 5x6 Packing Tape and reel DS10754 - Rev 6 - February 2020 For further information contact your local STMicroelectronics sales office. www.st.com STL120N8F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 80 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 120 Drain current (continuous) at TC = 100 °C 90 Drain current (pulsed) 480 Drain current (continuous) at Tpcb = 25 °C 23 Drain current (continuous) at Tpcb = 100 °C 17 IDM(2)(3) Drain current (pulsed) 92 A PTOT(1) Total dissipation at TC = 25 °C 140 W Total dissipation at Tpcb = 25 °C 4.8 W -55 to 175 °C Value Unit ID(1) IDM(1) (2) ID(3) (3) PTOT Tstg Storage temperature range TJ Operating junction temperature range A A A 1. This value is rated according to Rthj-c. 2. Pulse width is limited by safe operating area. 3. This value is rated according to Rthj-pcb. Table 2. Thermal data Symbol Rthj-pcb (1) Rthj-case Parameter Thermal resistance junction-pcb 31.3 Thermal resistance junction-case 1.05 °C/W 1. When mounted on a 1-inch² FR-4 board, 2oz Cu, t < 10 s. DS10754 - Rev 6 page 2/16 STL120N8F7 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. Static Symbol V(BR)DSS Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage VGS = 0 V, ID = 1 mA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 80 V 1 µA IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4.5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 11.5 A 4.0 4.8 mΩ Min. Typ. Max. Unit - 4600 - - 800 - - 64 - - 60 - - 24.7 - - 14.8 - 80 V 2.5 Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge RG Gate input resistance Test conditions VDS = 40 V, f = 1 MHz, VGS = 0 V VDD = 40 V, ID = 23 A, VGS = 10 V (see Figure 13. Test circuit for gate charge behavior) ID = 0 A, gate DC bias = 0 V, f = 1 MHz, magnitude of alternative signal = 20 mV - pF nC 2.0 Ω Unit Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 40 V, ID = 11.5 A, - 34.5 - Rise time RG = 4.7 Ω, VGS = 10 V - 16.8 - Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 60 - - 15.4 - Min. Typ. Max. Unit 1.2 V Fall time ns Table 6. Source-drain diode Symbol VSD (1) Parameter Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions VGS = 0 V, ISD = 23 A ISD = 23 A, di/dt = 100 A/µs, VDD = 64 V (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 48.6 ns - 65.6 nC - 2.7 A 1. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS10754 - Rev 6 page 3/16 STL120N8F7 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) K GIPG270715OD8FLZTH ) 10 µs D S( 10 2 on O lim per ite ati d on by in m th ax is . R ar e a is GIPG270715OD8FLSOA 100 µs 10 1 10 -1 1 ms T j = 175 °C T c = 25 °C single pulse 10 0 10 1 10 0 10 -1 10 ms V DS (V) 10 -2 10 -5 Figure 3. Output characteristics ID (A) GIPG270715OD8FLOCH V GS = 10 V V GS = 9 V 250 V GS = 8 V 200 150 V GS = 7 V 100 10 -4 10 -3 t p (s) 10 -2 Figure 4. Transfer characteristics ID (A) GIPG270715OD8FLTCH V DS = 2 V 250 200 150 100 V GS = 6 V 50 V GS = 5 V 0 0 2 4 6 8 V DS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG270715OD8FLQVG 50 0 0 2 4 6 8 V GS (V) Figure 6. Static drain-source on-resistance GIPD241020181347RID RDS(on) (mΩ) VDD = 40 V, ID = 23 A 12 DD D 5.00 VGS = 10V 10 4.60 8 4.20 6 3.80 4 3.40 2 0 0 DS10754 - Rev 6 10 20 30 40 50 60 70 Qg (nC) 3.00 0 20 40 60 80 100 120 ID (A) page 4/16 STL120N8F7 Electrical characteristics curves Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GIPG270715OD8FLCVR V GS(th) (norm.) C ISS GIPG270715OD8FLVTH I D = 250 µA 1.1 1.0 10 3 0.9 C OSS 0.8 0.7 10 2 0.6 C RSS f = 1 MHz 10 1 10 -1 10 0 0.5 0.4 -75 V DS (V) 10 1 75 V (BR)DSS (norm.) GIPG270715OD8FLRON 2.0 25 125 175 T j (°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature R DS(on) (norm.) -25 V GS = 10 V GIPG270715OD8FLBDV I D = 1 mA 1.04 1.8 1.02 1.6 1.4 1.00 1.2 0.98 1.0 0.96 0.8 0.6 -75 -25 25 75 125 175 0.94 -75 T j (°C) -25 25 75 125 175 T j (°C) Figure 11. Source-drain diode forward characteristics V SD (V) 1.0 0.9 GIPG270715OD8FLSDF T j = -55 °C T j = 25 °C 0.8 0.7 0.6 0 DS10754 - Rev 6 T j = 175 °C 20 40 60 80 100 I SD (A) page 5/16 STL120N8F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10754 - Rev 6 page 6/16 STL120N8F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 type C package information Figure 18. PowerFLAT 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_Rev20 DS10754 - Rev 6 page 7/16 STL120N8F7 PowerFLAT 5x6 type C package information Table 7. PowerFLAT 5x6 type C package mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS10754 - Rev 6 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 8/16 STL120N8F7 PowerFLAT 5x6 type C SUBCON package information 4.2 PowerFLAT 5x6 type C SUBCON package information Figure 19. PowerFLAT 5x6 type C SUBCON package outline 8472137_SUBCON_998G_REV4 8472137_SUBCON_998G_REV4 DS10754 - Rev 6 page 9/16 STL120N8F7 PowerFLAT 5x6 type C SUBCON package information Table 8. PowerFLAT 5x6 type C SUBCON package mechanical data Dim. A mm Min. Typ. Max. 0.90 0.95 1.00 A1 b 0.02 0.35 b1 c 0.40 0.30 0.21 0.25 D 0.34 5.10 D1 4.80 4.90 5.00 D2 4.01 4.21 4.31 e 1.17 1.27 1.37 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.54 3.64 3.74 E4 0.15 0.25 0.35 E5 0.26 0.36 0.46 H 0.51 0.61 0.71 K 0.95 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 L2 DS10754 - Rev 6 0.45 0.10 P 1.00 1.10 1.20 θ 8° 10° 12° page 10/16 STL120N8F7 PowerFLAT 5x6 type C SUBCON package information Figure 20. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_20 DS10754 - Rev 6 page 11/16 STL120N8F7 PowerFLAT 5x6 packing information 4.3 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS10754 - Rev 6 page 12/16 STL120N8F7 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS10754 - Rev 6 page 13/16 STL120N8F7 Revision history Table 9. Document revision history Date Revision 09-Dec-2014 1 Changes First release. Text and formatting changes throughout document. Datasheet status promoted from preliminary data to production data. 27-Jul-2015 2 In section Electrical characteristics: - updated tables Dynamic, Switching times and Source-drain diode - added section Electrical characteristics (curves) 25-Jan-2016 3 09-Feb-2016 4 Inserted RG parameter in Dynamic. Updated Table 4: "Static" and Section 4.1: "PowerFLAT™ 5x6 type C package information". Removed maturity status indication from cover page. 02-Nov-2018 5 Updated title and features in cover page. Updated Table 3. Static and Figure 6. Static drain-source on-resistance. Minor text changes. 25-Feb-2020 DS10754 - Rev 6 6 Updated Section 4 Package information. Minor text changes. page 14/16 STL120N8F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.1 PowerFLAT 5x6 type C package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 PowerFLAT 5x6 type C SUBCON package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DS10754 - Rev 6 page 15/16 STL120N8F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS10754 - Rev 6 page 16/16