STL12N60M2

STL12N60M2 N-channel 600 V, 0.400 Ω typ., 6.5 A MDmesh™ M2 Power MOSFET in a PowerFLAT 5x6 HV package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STL12N60M2 600 V 0.495 Ω 6.5 A 52 W • • • • 1 2 3 4 PowerFLAT™ 5x6 HV Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications Figure 1: Internal schematic diagram • Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packing STL12N60M2 12N60M2 PowerFLAT 5x6 HV Tape and reel May 2015 DocID027900 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STL12N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 5x6 HV package information .................................... 10 4.2 PowerFLAT™ 5x6 packing information ........................................... 12 Revision history ............................................................................ 14 DocID027900 Rev 1 STL12N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS (1) ID (2) IDM PTOT Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 6.5 Drain current (continuous) at Tcase = 100 °C 4.1 Drain current (pulsed) 26 A W Total dissipation at Tcase = 25 °C 52 dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature Tj Operating junction temperature A V/ns -55 to 150 °C Value Unit Notes: (1) (2) Limited by maximum junction temperature. Pulse width is limited by safe operating area. (3) ISD ≤ 6.5 A, di/dt=400 A/μs; VDS(peak) < V(BR)DSS, VDD = 80% V(BR)DSS. (4) VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.4 Thermal resistance junction-pcb 50 Rthj-pcb (1) °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 4: Avalanche characteristics Symbol (1) IAR (2) EAR Parameter Value Unit Avalanche current, repetitive or not repetitive 1.6 A Single pulse avalanche energy 120 mJ Notes: (1) (2) Pulse width limited by Tjmax. starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID027900 Rev 1 3/15 Electrical characteristics 2 STL12N60M2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C 100 ±10 µA 3 4 V 0.400 0.495 Ω Min. Typ. Max. Unit - 538 - - 29 - - 1.1 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4.5 A 2 µA Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V pF Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 106 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge - 16 - Qgs Gate-source charge - 2.3 - Qgd Gate-drain charge VDD = 400 V, ID = 9 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") - 8.5 - Coss eq. (1) nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 300 V, ID = 4.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 9.2 - - 9.2 - - 56 - - 18 - DocID027900 Rev 1 Unit ns STL12N60M2 Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 9 A (1) Source-drain current (pulsed) - 36 A (2) Forward on voltage VGS = 0 V, ISD = 9 A - 1.6 V trr Reverse recovery time - 284 ns Qrr Reverse recovery charge - 2.4 µC IRRM Reverse recovery current ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 17 A - 404 ns - 3.5 µC - 17.5 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 9 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027900 Rev 1 5/15 Electrical characteristics 2.1 6/15 STL12N60M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027900 Rev 1 STL12N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature AM03184v1 VGS(th) (norm) 1.10 1.00 ID = 250 µA 0.90 0.80 0.70 -50 0 50 100 Tj(°C) Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source- drain diode forward characteristics DocID027900 Rev 1 7/15 Test circuits 3 STL12N60M2 Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/15 DocID027900 Rev 1 STL12N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID027900 Rev 1 9/15 Package information 4.1 STL12N60M2 PowerFLAT™ 5x6 HV package information Figure 20: PowerFLAT™ 5x6 HV package outline b (x8) BOTTOM VIEW K L e Resin protrusion D2 A E2 PIN #1 ID A2 A1 SEATING PLANE SIDE VIEW E D Resin protrusion TOP VIEW 8368143_Rev_B 10/15 DocID027900 Rev 1 STL12N60M2 Package information Table 9: PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 3.10 3.20 3.30 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 21: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 0.5 0.73 3.04 1.9 6.4 3.77 5.4 0.77 4.31 8368143_Rev_B_footprint DocID027900 Rev 1 11/15 Package information 4.2 STL12N60M2 PowerFLAT™ 5x6 packing information Figure 22: PowerFLAT™ 5x6 tape (dimensions are in mm) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y F(5.50±0.1)(III) R Bo (5.30±0.1) C L EF D1 Ø1.5 MIN. REF .R0 W(12.00±0.3) 0. 20 Do Ø1.55±0.05 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID027900 Rev 1 8234350_Tape_rev_C STL12N60M2 Package information Figure 24: PowerFLAT™ 5x6 reel DocID027900 Rev 1 13/15 Revision history 5 STL12N60M2 Revision history Table 10: Document revision history 14/15 Date Revision 22-May-2015 1 DocID027900 Rev 1 Changes First release. STL12N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027900 Rev 1 15/15