STL12N60M6

STL12N60M6 Datasheet N-channel 600 V, 390 mΩ typ., 6.4 A MDmesh™ M6 Power MOSFET in a PowerFLAT™ 5x6 HV package Features 1 2 3 4 PowerFLAT™ 5x6 HV D(5, 6, 7, 8) 8 7 5 6 Order code VDS @ TJmax RDS(on) max. ID PTOT STL12N60M6 650 V 490 mΩ 6.4 A 48 W • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • G(4) 1 2 3 4 Top View S(1, 2, 3) Switching applications LLC converters Boost PFC converters AM15540v1 Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status STL12N60M6 Product summary Order code STL12N60M6 Marking 12N60M6 Package PowerFLAT™ 5x6 HV Packing Tape and Reel DS12869 - Rev 1 - January 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL12N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 6.4 Drain current (continuous) at Tcase = 100 °C 4 IDM (1) Drain current (pulsed) 24 A PTOT Total power dissipation at Tcase = 25 °C 48 W IAR (2) Avalanche current, repetitive or not repetitive 1.8 A EAS (3) Single pulse avalanche energy 130 mJ dv/dt(4) Peak diode recovery voltage slope 15 dv/dt(5) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID Tj Parameter Operating junction temperature range -55 to 150 A V/ns °C 1. Pulse width is limited by safe operating area. 2. Pulse width limited by Tjmax. 3. starting Tj = 25 °C, ID = IAR, VDD = 50 V. 4. ISD ≤ 6.4 A, di/dt = 400 A/μs; VDS peak < V(BR)DSS, VDD = 400 V. 5. VDS ≤ 480 V. Table 2. Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case 2.6 Rthj-pcb (1) Thermal resistance junction-pcb 50 Unit °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. DS12869 - Rev 1 page 2/15 STL12N60M6 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 3. Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) 100 ±10 µA 4 4.75 V 390 490 mΩ Min. Typ. Max. Unit - 452 - - 39.4 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3.2 A 3.25 µA 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance - 4.5 - Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 85 - pF Ω Coss eq. (1) RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6 - Qg Total gate charge VDD = 480 V, ID = 9 A, - 12.3 - Qgs Gate-source charge - 3 - Qgd Gate-drain charge VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) - 6.5 - pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 5. Switching times Symbol td(on) tr td(off) tf DS12869 - Rev 1 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 4.5 A, - 16.6 - Rise time RG = 4.7 Ω, VGS = 10 V (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 6.4 - - 23.9 - - 9.9 - Turn-off delay time Fall time Unit ns page 3/15 STL12N60M6 Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 6.4 A Source-drain current (pulsed) - 24 A 1.6 V Forward on voltage VGS = 0 V, ISD = 6.4 A - trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs, - 174 ns Qrr Reverse recovery charge - 1.27 µC IRRM Reverse recovery current VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 14.6 A VSD trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs, - 241 ns Qrr Reverse recovery charge - 1.9 µC IRRM Reverse recovery current VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 15.6 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12869 - Rev 1 page 4/15 STL12N60M6 Electrical characteristics curves 2.1 Electrical characteristics curves Figure 1. Safe operating area ID (A) Operation in this area is limited by R DS(on) Figure 2. Thermal impedance GIPG131220181143SOA K ZthPowerFlat_5x6_19 d=0.5 0.2 tp =1 µs 10 1 10 -1 0.1 0.05 0.02 0.01 tp =10 µs tp =100 µs 10 0 TJ≤150 °C TC=25 °C VGS=10 V single pulse 10 -1 10 -1 10 10 0 tp =10 ms VDS (V) 2 10-3 -6 10 Figure 3. Output characteristics ID (A) VGS = 10 V 20 VGS = 9 V 24 VGS = 8 V 20 VGS = 7 V 8 VGS = 6 V 2 4 6 8 VGS = 5 V 10 12 14 16 18 VDS (V) Figure 5. Gate charge vs gate-source voltage Qg 4 100 2 DS12869 - Rev 1 6 4 5 6 7 8 9 VGS (V) GIPG131220181124RID VGS =10 V 410 400 200 4 3 Figure 6. Static drain-source on-resistance 420 6 2 2 8 Qgd Qgs 0 1 12 10 VDS 4 RDS(on) (mΩ) 300 0 0 VDS =20 V 12 (V) GIPG131220181134QVG VGS VDD = 480 V ID = 9A 500 400 GIPG131220181133TCH 8 4 600 10-2 10-1 100 tp(s) 16 12 VDS (V) 10-3 ID (A) 16 0 0 10-5 10-4 Figure 4. Transfer characteristics GIPG131220181132OCH 24 Single pulse tp =1 ms 10 1 10-2 8 10 12 14 0 Qg (nC) 390 380 370 0 1 2 3 4 5 6 ID (A) page 5/15 STL12N60M6 Electrical characteristics curves Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) GIPG131220181130CVR ADG131220181241EOS 4 10 3 CISS 3 10 2 2 10 1 10 0 10 -1 COSS f = 1 MHz 10 0 10 1 10 2 CRSS 1 VDS (V) 0 0 Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GIPG131220181031VTH ID = 250 μA 1.1 300 400 500 VDS (V) RDS(on) (norm.) GIPG131220181123RON VGS = 10 V 1.8 1.4 0.9 1.0 0.8 0.6 0.7 -25 25 75 125 TJ (°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) 1.08 200 Figure 10. Normalized on-resistance vs temperature 2.2 1.0 0.6 -75 100 GIPG131220181128BDV ID = 1 mA 0.2 -75 -25 25 75 125 TJ (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GIPG131220181130SDF 1.1 TJ = -50 °C 1.0 1.04 TJ = 25 °C 0.9 1.00 0.8 0.96 0.7 0.92 0.88 -75 DS12869 - Rev 1 TJ = 150 °C 0.6 -25 25 75 125 TJ (°C) 0.5 0 1 2 3 4 5 6 ISD (A) page 6/15 STL12N60M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD IG= CONST VGS + pulse width RG VGS D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12869 - Rev 1 page 7/15 STL12N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12869 - Rev 1 page 8/15 STL12N60M6 PowerFLAT™ 5x6 HV package information 4.1 PowerFLAT™ 5x6 HV package information Figure 19. PowerFLAT™ 5x6 HV package outline 8368143_Rev_4 DS12869 - Rev 1 page 9/15 STL12N60M6 PowerFLAT™ 5x6 HV package information Table 7. PowerFLAT™ 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS12869 - Rev 1 page 10/15 STL12N60M6 PowerFLAT™ 5x6 packing information 4.2 PowerFLAT™ 5x6 packing information Figure 21. PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification DS12869 - Rev 1 page 11/15 STL12N60M6 PowerFLAT™ 5x6 packing information Figure 23. PowerFLAT™ 5x6 reel DS12869 - Rev 1 page 12/15 STL12N60M6 Revision history Table 8. Document revision history DS12869 - Rev 1 Date Revision 13-Jan-2019 1 Changes First release. page 13/15 STL12N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT™ 5x6 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT™ 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12869 - Rev 1 page 14/15 STL12N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12869 - Rev 1 page 15/15