STL130N8F7

STL130N8F7 Datasheet N-channel 80 V, 3.0 mΩ typ., 120 A STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Features PowerFLAT 5x6 D(5, 6, 7, 8) 8 7 5 6 Order code VDS RDS(on) max. ID PTOT STL130N8F7 80 V 3.6 mΩ 120 A 135 W • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications G(4) Description 1 2 3 4 Top View S(1, 2, 3) This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. AM15540v2 Product status link STL130N8F7 Product summary Order code STL130N8F7 Marking 130N8F7 Package PowerFLAT 5x6 Packing Tape and reel DS9349 - Rev 5 - February 2020 For further information contact your local STMicroelectronics sales office. www.st.com STL130N8F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 80 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 120 Drain current (continuous) at TC = 100 °C 93 Drain current (continuous) at Tpcb = 25 °C 26 Drain current (continuous) at Tpcb = 100 °C 19 IDM(1)(3) Drain current (pulsed) 480 A IDM(2)(3) Drain current (pulsed) 104 A PTOT (1) Total power dissipation at TC = 25 °C 135 W Total power dissipation at Tpcb = 25 °C 4.8 W Single pulse avalanche energy 515 mJ -55 to 175 °C Value Unit Thermal resistance junction-case 1.1 °C/W Thermal resistance junction-pcb 31.3 °C/W ID(1) ID(2) PTOT (2) EAS(4) Tstg Storage temperature range TJ Operating junction temperature range A A 1. This value is rated according to Rthj-case and is limited by package. 2. This value is rated according to Rthj-pcb. 3. Pulse width is limited by safe operating area. 4. Starting TJ = 25 °C, ID = 18.5 A, VDD = 50 V. Table 2. Thermal data Symbol Rthj-case (1) Rthj-pcb Parameter 1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s. DS9349 - Rev 5 page 2/16 STL130N8F7 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 3. On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 250 µA Typ. 80 Zero gate voltage drain current IGSS Gate body leakage current VDS = 0 V, VGS = 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 13 A VGS = 0 V, VDS = 80 V, TJ = 125 Unit V VGS = 0 V, VDS = 80 V IDSS Max. 1 µA 10 µA 100 nA 4.5 V 3.0 3.6 mΩ Min. Typ. Max. Unit - 6340 - pF - 1195 - pF - 105 - pF - 96 - nC - 29 - nC - 26 - nC Min. Typ. Max. Unit °C(1) 2.5 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VGS = 0 V, VDS = 40 V, f = 1 MHz VDD = 40 V, ID = 26 A, VGS = 0 to 10 V (see Figure 13. Test circuit for gate charge behavior) Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 40 V, ID = 13 A, - 26 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 51 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 82 - ns - 44 - ns Min. Typ. Max. Unit 1.2 V Fall time Table 6. Source-drain diode Symbol VSD(1) Parameter Test conditions Forward on voltage ISD = 26 A, VGS = 0 V - trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs, - 58 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 92 nC IRRM Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 3.2 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS9349 - Rev 5 page 3/16 STL130N8F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Normalized thermal impedance Figure 1. Safe operating area ID (A) K GADG301020170838SOA Operation in this area GADG301020170838ZTH δ = 0.5 102 δ = 0.2 δ = 0.1 tp =40µs 101 δ = 0.05 10 -1 δ = 0.02 tp =100µs 100 T ≤ 175 °C T c = 25°C single pulse is limited by RDS(on)j 10-1 10-1 100 δ = 0.01 Single pulse tp =1ms tp =10ms VDS (V) 101 10 -2 10 -5 Figure 3. Output characteristics GIP D120920131428FS R ID (A) VGS = 10V 160 140 5V 100 60 60 4V 0 0 6 4 2 8 VDS (V) Figure 5. Gate charge vs gate-source voltage GIP D120920131444FS R VDS = 2V 100 80 20 tp (s) 10 -1 120 80 40 10 -2 ID (A) 180 140 6V 10 -3 Figure 4. Transfer characteristics 160 120 10 -4 40 20 0 0 1 2 3 4 5 6 7 8 VGS (V) Figure 6. Static drain-source on-resistance GIP D120920131452FS R VGS (V) 12 VDD= 40V ID= 26A 10 8 6 3.00 4 2 0 0 DS9349 - Rev 5 20 40 60 80 100 Q g (nC) page 4/16 STL130N8F7 Electrical characteristics (curves) Figure 8. Normalized V(BR)DSS vs temperature Figure 7. Capacitance variations GIP D120920131512FS R C (pF) 8000 GIPD120920131527FSR 7000 Ciss 6000 5000 1.00 4000 3000 2000 1000 0 0 10 20 30 40 50 60 Coss Crss 70 VDS(V) Figure 9. Normalized gate threshold voltage vs temperature Figure 10. Normalized on-resistance vs temperature 1.0 1.0 Figure 11. Source-drain diode forward characteristics GIP D130920131009FS R VDS (V) TJ= -55°C 0.9 0.8 TJ= 25°C 0.7 0.6 TJ= 175°C 0.5 0.4 DS9349 - Rev 5 4 8 12 16 20 24 ID(A) page 5/16 STL130N8F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS9349 - Rev 5 page 6/16 STL130N8F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 type C package information Figure 18. PowerFLAT 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_Rev20 DS9349 - Rev 5 page 7/16 STL130N8F7 PowerFLAT 5x6 type C package information Table 7. PowerFLAT 5x6 type C package mechanical data Dim. mm Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e DS9349 - Rev 5 Typ. 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 θ 0° 0.15 6.35 0.25 12° page 8/16 STL130N8F7 PowerFLAT 5x6 type C SUBCON package information 4.2 PowerFLAT 5x6 type C SUBCON package information Figure 19. PowerFLAT 5x6 type C SUBCON package outline 8472137_SUBCON_998G_REV4 8472137_SUBCON_998G_REV4 DS9349 - Rev 5 page 9/16 STL130N8F7 PowerFLAT 5x6 type C SUBCON package information Table 8. PowerFLAT 5x6 type C SUBCON package mechanical data Dim. A mm Min. Typ. Max. 0.90 0.95 1.00 A1 b 0.02 0.35 b1 c 0.40 0.30 0.21 0.25 D 0.34 5.10 D1 4.80 4.90 5.00 D2 4.01 4.21 4.31 e 1.17 1.27 1.37 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.54 3.64 3.74 E4 0.15 0.25 0.35 E5 0.26 0.36 0.46 H 0.51 0.61 0.71 K 0.95 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 L2 DS9349 - Rev 5 0.45 0.10 P 1.00 1.10 1.20 θ 8° 10° 12° page 10/16 STL130N8F7 PowerFLAT 5x6 type C SUBCON package information Figure 20. PowerFLAT 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_20 DS9349 - Rev 5 page 11/16 STL130N8F7 PowerFLAT 5x6 packing information 4.3 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS9349 - Rev 5 page 12/16 STL130N8F7 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS9349 - Rev 5 page 13/16 STL130N8F7 Revision history Table 9. Document revision history Date Revision 21-May-2013 1 23-Sep-2013 2 Changes First release Document status promoted form preliminary to production data. Inserted Section 2.1: Electrical characteristics (curves). Modified: title and description Modified: ID and PTOT values in cover page 25-Jul-2014 3 Updated: Figure 13, 14, 15 and 16 Updated: Section 4: Package mechanical data Minor text changes Updated title and features table on cover page. Updated Table 2: "Absolute maximum ratings" and Table 7: "Source-drain diode". 03-Nov-2017 4 Updated Figure 2: "Safe operating area" and Figure 3: "Normalized thermal impedance". Updated Section 4.1: "PowerFLAT™ 5x6 type C package information". Minor text changes 26-Feb-2020 DS9349 - Rev 5 5 Updated Section 4 Package information. Minor text changes. page 14/16 STL130N8F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.1 PowerFLAT 5x6 type C package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 PowerFLAT 5x6 type C SUBCON package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DS9349 - Rev 5 page 15/16 STL130N8F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS9349 - Rev 5 page 16/16