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STL13N60DM2

STL13N60DM2

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    PowerVDFN8

  • 描述:

    N-CHANNEL600V,0.350OHMTYP.,

  • 数据手册
  • 价格&库存
STL13N60DM2 数据手册
STL13N60DM2 N-channel 600 V, 0.350 Ω typ., 8 A MDmesh™ DM2 Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet - production data Features   1 2 3 4     PowerFLAT™ 5x6 HV Order code VDS RDS(on) max. ID STL13N60DM2 600 V 0.370 Ω 8A Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Figure 1: Internal schematic diagram Applications D(5, 6, 7, 8) 8 7 6 5  Switching applications Description G(4) 1 S(1, 2, 3) 2 3 4 This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Top View Table 1: Device summary Order code Marking Package Packing STL13N60DM2 13N60DM2 PowerFLAT™ 5x6 HV Tape and reel December 2016 DocID029284 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STL13N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 5 2/15 4.1 PowerFLAT™ 5x6 HV package information .................................... 10 4.2 Packing information......................................................................... 12 Revision history ............................................................................ 14 DocID029284 Rev 2 STL13N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS Value Unit Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 8(1) A ID Drain current (continuous) at TC= 100 °C 5 A IDM(2) Drain current (pulsed) 32 A PTOT Total dissipation at TC = 25 °C 52 W dv/dt(3) Peak diode recovery voltage slope 40 V/ns dv/dt(4) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range - 55 to 150 Tj Operating junction temperature range 150 °C Notes: (1)The value is limited by package. (2)Pulse (3)I SD (4)V width limited by safe operating area. ≤ 8 A, di/dt ≤ 400 A/µs; VDS peak < V(BR)DSS, VDD = 400 V DS ≤ 480 V Table 3: Thermal data Symbol Rthj-case Rthj-pcb Parameter Thermal resistance junction-case max Thermal resistance junction-pcb Value Unit 2.40 °C/W 59 °C/W max(1) Notes: (1)When mounted on 1 inch2 FR-4, 2 Oz copper board Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 2.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 340 mJ DocID029284 Rev 2 3/15 Electrical characteristics 2 STL13N60DM2 Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1.5 µA VGS = 0 V, VDS = 600 V, TC = 125 °C(1) 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 0.350 0.370 Ω Min. Typ. Max. Unit - 730 - pF - 38 - pF - 0.9 - pF 3 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 V to 480 V, VGS = 0 V - 70 - pF RG Intrinsic gate resistance f = 1 MHz, ID=0 A - 5.1 - Ω Qg Total gate charge - 19 - nC Qgs Gate-source charge - 4.4 - nC Qgd Gate-drain charge VDD = 480 V, ID = 11 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 9.9 - nC VDS= 100 V, f = 1 MHz, VGS = 0 V Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 300 V, ID = 5.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 12.3 - ns - 4.8 - ns - 42.5 - ns - 10.6 - ns DocID029284 Rev 2 STL13N60DM2 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 8 A ISDM(1) Source-drain current (pulsed) - 32 A VSD (2) Forward on voltage VGS = 0 V, ISD = 8 A - 1.6 V trr Reverse recovery time - 90 ns Qrr Reverse recovery charge - 252 nC IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 5.6 A ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 170 ns - 667 ns - 8.6 A Test conditions Min. Typ. Max. Unit IGS = ± 1 mA, ID = 0 A ±30 - - V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width is limited by safe operating area (2)Pulse test: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V(BR)GSO Parameter Gate-source breakdown voltage The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID029284 Rev 2 5/15 Electrical characteristics 2.1 STL13N60DM2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID029284 Rev 2 STL13N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Output capacitance stored energy DocID029284 Rev 2 7/15 Test circuits 3 STL13N60DM2 Test circuits Figure 15: Test circuit for gate charge behavior Figure 14: Test circuit for resistive load switching times Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/15 DocID029284 Rev 2 Figure 19: Switching time waveform STL13N60DM2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID029284 Rev 2 9/15 Package mechanical data 4.1 STL13N60DM2 PowerFLAT™ 5x6 HV package information Figure 20: PowerFLAT™ 5x6 HV package outline 8368143_Rev_3 10/15 DocID029284 Rev 2 STL13N60DM2 Package mechanical data Table 10: PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.10 5.20 5.30 E 6.05 6.15 6.25 E2 3.10 3.20 3.30 D2 4.30 4.40 4.50 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 21: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_3_footprint DocID029284 Rev 2 11/15 Package mechanical data 4.2 STL13N60DM2 Packing information Figure 22: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID029284 Rev 2 STL13N60DM2 Package mechanical data Figure 24: PowerFLAT™ 5x6 reel DocID029284 Rev 2 13/15 Revision history 5 STL13N60DM2 Revision history Table 11: Document revision history 14/15 Date Revision Changes 02-May-2016 1 First release. 07-Dec-2016 2 Document status promoted from preliminary to production data. DocID029284 Rev 2 STL13N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029284 Rev 2 15/15
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