STL13N60M6

STL13N60M6 Datasheet N-channel 600 V, 330 mΩ typ., 7 A, MDmesh M6 Power MOSFET in a PowerFLAT 5x6 HV package Features 1 2 3 4 PowerFLAT 5x6 HV D(5, 6, 7, 8) Order code VDS RDS(on) max. ID PTOT STL13N60M6 600 V 415 mΩ 7A 52 W • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • G(4) Switching applications LLC converters Boost PFC converters Description S(1, 2, 3) AM15540v7 The new MDmesh M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STL13N60M6 Product summary Order code STL13N60M6 Marking 13N60M6 Package PowerFLAT™ 5x6 HV Packing Tape and reel DS12870 - Rev 2 - May 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL13N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 7 Drain current (continuous) at Tcase = 100 °C 4.5 IDM(1) Drain current (pulsed) 28 A PTOT Total power dissipation at Tcase = 25 °C 52 W IAR(2) Avalanche current, repetitive or not repetitive 2 A EAS(3) Single pulse avalanche energy 140 mJ dv/dt(4) Peak diode recovery voltage slope 15 dv/dt(5) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range ID Tj Operating junction temperature range A V/ns -55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. Pulse width limited by Tjmax. 3. Starting Tj = 25 °C, ID = IAR, VDD = 50 V. 4. ISD ≤ 7 A, di/dt = 400 A/μs, VDS(peak) < V(BR)DSS, VDD = 400 V 5. VDS ≤ 480 V Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.4 Rthj-pcb(1) Thermal resistance junction-pcb 50 °C/W 1. When mounted on an 1-inch² FR-4, 2 Oz copper board. DS12870 - Rev 2 page 2/15 STL13N60M6 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 3. Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 IDSS Zero gate voltage drain current VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) 100 IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 4.75 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 3.5 A 330 415 mΩ Min. Typ. Max. Unit - 509 - - 34.4 - - 4.2 - 3.25 µA 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 94 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.6 - Ω Qg Total gate charge VDD = 480 V, ID = 10 A, - 13 - Qgs Gate-source charge VGS = 0 to 10 V - 3.4 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 6.4 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 5. Switching times Symbol td(on) tr td(off) tf DS12870 - Rev 2 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 5 A, - 15.8 - Rise time RG = 4.7 Ω, VGS = 10 V - 6.5 - Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 25.5 - - 9.4 - Fall time Unit ns page 3/15 STL13N60M6 Electrical characteristics Table 6. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7 A Source-drain current (pulsed) - 28 A 1.6 V Forward on voltage VGS = 0 V, ISD = 7 A - trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 182 ns Qrr Reverse recovery charge VDD = 60 V - 1.35 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 14.8 A trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs, - 253 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 2 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 16 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12870 - Rev 2 page 4/15 STL13N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG171220181338SOA K ZthPowerFlat_5x6_19 d=0.5 0.2 tp =1 μs 10 1 Operation in this area is limited by RDS(on) tp =10 µs 10-1 0.1 0.05 0.02 0.01 tp =100 µs 10 0 tp =1 ms 10-2 Single pulse Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V tp =10 ms 10 -1 10 -1 10 0 10 1 VDS (V) 10 2 10-3 -6 10 Figure 3. Output characteristics ID (A) 24 ID (A) VGS = 9 V 24 20 20 16 16 VGS = 7 V 8 4 4 VGS = 6 V 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage 600 VDD = 480 V, ID = 10 A Qg 12 370 8 Qgd Qgs 6 200 4 100 2 DS12870 - Rev 2 3 6 6 7 8 9 VGS (V) GADG171220181339RID 360 350 VGS = 10 V 340 300 0 0 5 Figure 6. Static drain-source on-resistance RDS(on) (mΩ) 10 VDS 0 4 (V) GADG131220181021QVG VGS 500 400 VDS = 18 V 12 8 VDS (V) 10-2 10-1 100 tp(s) GADG171220181338TCH VGS = 8 V 12 10-3 Figure 4. Transfer characteristics GADG171220181338OCH VGS = 10 V 10-5 10-4 9 12 15 0 Qg (nC) 330 320 310 300 0 1 2 3 4 5 6 7 ID (A) page 5/15 STL13N60M6 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) GADG131220181023CVR GADG131220181023EOS 5 10 3 CISS 10 2 10 1 10 0 10 -1 3 COSS 2 CRSS 1 VDS (V) 0 0 f = 1 MHz 10 0 10 1 10 2 Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GADG131220181021VTH 100 200 300 400 VDS (V) RDS(on) (norm.) GADG131220181022RON VGS = 10 V 1.4 0.9 ID = 250 µA 1.0 0.8 0.6 0.7 -25 25 75 125 Tj (°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG131220181022BDV 0.2 -75 -25 25 75 125 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG131220181022SDF 1.1 1.08 TJ = -50 °C 1.0 1.04 TJ = 25 °C 0.9 1.00 ID = 1 mA 0.8 TJ = 150 °C 0.96 0.7 0.92 DS12870 - Rev 2 600 Figure 10. Normalized on-resistance vs temperature 1.8 1.0 0.88 -75 500 2.2 1.1 0.6 -75 4 0.6 -25 25 75 125 Tj (°C) 0.5 0 1 2 3 4 5 6 7 ISD (A) page 6/15 STL13N60M6 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD IG= CONST VGS + pulse width RG VGS D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12870 - Rev 2 page 7/15 STL13N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS12870 - Rev 2 page 8/15 STL13N60M6 PowerFLAT 5x6 HV package information 4.1 PowerFLAT 5x6 HV package information Figure 19. PowerFLAT 5x6 HV package outline 8368143_Rev_4 DS12870 - Rev 2 page 9/15 STL13N60M6 PowerFLAT 5x6 HV package information Table 7. PowerFLAT 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS12870 - Rev 2 page 10/15 STL13N60M6 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS12870 - Rev 2 page 11/15 STL13N60M6 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS12870 - Rev 2 page 12/15 STL13N60M6 Revision history Table 8. Document revision history DS12870 - Rev 2 Date Version Changes 18-Dec-2018 1 First release. 20-May-2019 2 Updated Table 3. Static. Updated Figure 14. Test circuit for gate charge behavior. Minor text changes. page 13/15 STL13N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12870 - Rev 2 page 14/15 STL13N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12870 - Rev 2 page 15/15