STL13N65M2

STL13N65M2 N-channel 650 V, 0.365 Ω typ., 6.5 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet − production data Features Order code VDS RDS(on) max ID STL13N65M2 650 V 0.475 Ω 6.5 A • Extremely low gate charge • Excellent output capacitance (COSS) profile 1 2 • 100% avalanche tested 3 4 • Zener-protected PowerFLAT™ 5x6 HV Applications • Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) Description 8 7 6 5 1 2 3 4 G(4) S(1, 2, 3) This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Top View AM15540v2 Table 1. Device summary Order code Marking Package Packaging STL13N65M2 13N65M2 PowerFLAT™ 5x6 HV Tape and reel December 2014 This is information on a product in full production. DocID027319 Rev 1 1/16 www.st.com Contents STL13N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 8 DocID027319 Rev 1 STL13N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Value Unit Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 6.5 A ID Drain current (continuous) at TC = 100 °C 4.1 A IDM (1) Drain current (pulsed) 26 A PTOT Total dissipation at TC = 25 °C 52 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns VGS dv/dt (2) dv/dt(3) Tstg Tj Parameter Storage temperature - 55 to 150 °C Max. operating junction temperature 150 1. Pulse width limited by safe operating area. 2. ISD ≤ 6.5 A, di/dt ≤ 400 A/µs; V DS peak < V(BR)DSS, VDD=400 V. 3. VDS ≤ 520 V Table 3. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 2.4 °C/W Rthj-pcb Thermal resistance junction-pcb max(1) 59 °C/W Value Unit 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 110 mJ DocID027319 Rev 1 3/16 16 Electrical characteristics 2 STL13N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0 V, ID = 1 mA Min. Typ. Max. Unit 650 V VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC=125 °C 100 µA VDS = 0 V, VGS = ± 25 V ±10 µA 3 4 V 0.365 0.475 Ω Min. Typ. Max. Unit - 590 - pF - 27.5 - pF - 1.1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 3 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 520 V - 168.5 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 6.5 - Ω Qg Total gate charge - 17 - nC - 3.3 - nC - 7 - nC Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 V, VDS = 100 V, f = 1 MHz, VDD = 520 V, ID = 10 A, VGS = 10 V (see Figure 15) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID027319 Rev 1 STL13N65M2 Electrical characteristics Table 7. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 325 V, ID = 5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and 19) Rise time td(off) tf Turn-off delay time Fall time Min. Typ. Max. Unit - 11 - ns - 7.8 - ns - 38 - ns - 12 - ns Min. Typ. Table 8. Source drain diode Symbol Parameter Test conditions Max. Unit Source-drain current - 6.5 A ISDM (1) Source-drain current (pulsed) - 26 A VSD (2) Forward on voltage - 1.6 V ISD trr VGS = 0 V, ISD = 6.5 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 10 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16) ISD = 10 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16) - 312 ns - 2.7 µC - 17.5 A - 464 ns - 4 µC - 17.5 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027319 Rev 1 5/16 16 Electrical characteristics 2.1 STL13N65M2 Electrical characteristics (curves) Figure 2. Safe operating area ,' $ Figure 3. Thermal impedance *,3*$/6 =WK3RZHU)ODWB[B . į    —V 6 RQ 2 /L SHU P DW LWH LR G QL E\ Q P WKL D[ VD 5 UH D ' LV     —V  PV PV   6LQJOHSXOVH 7M ƒ& 7F ƒ& 6LQJOHSXOVH   WS Ϩ   9'69   Figure 4. Output characteristics ,' $  =WK . 5 WK-F į W SϨ   *,3*$/6 9*6 9               WSV Figure 5. Transfer characteristics ,' $  *,3*$/6  9'6 9 9         9     9'69 Figure 6. Normalized VBR(DSS) vs temperature *,3*$/6 9%5'66 QRUP      9*69  Figure 7. Static drain-source on-resistance 5'6RQ ȍ *,3*$/6      ,' P$  9*6 9         6/16    7-ƒ&  DocID027319 Rev 1        ,'$ STL13N65M2 Electrical characteristics Figure 8. Gate charge vs gate-source voltage 9*6 9  *,3*$/6 9'6 9  9'6  *,3*$/6 & S)  &LVV  9'' 9 ,' $  Figure 9. Capacitance variations         &RVV    4JQ&       Figure 10. Normalized gate threshold voltage vs temperature 9*6WK QRUP *,3*$/6 &UVV    9'69   Figure 11. Normalized on-resistance vs temperature *,3*$/6 5'6RQ QRUP     ,' —$             7-ƒ& Figure 12. Source-drain diode forward characteristics 96' 9 *,3*$/6 7- ƒ&   ,' $ 9*6 9     7-ƒ& Figure 13. Output capacitance stored energy (266 —- *,3*$/6    7- ƒ&   7- ƒ&            ,6'$   DocID027319 Rev 1       9'69 7/16 16 Test circuits 3 STL13N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit 9'' 9 μF VDD VD VGS ,* &2167 9L 9 9*0$; RG Nȍ Q) 3.3 μF 2200 RL Nȍ  —) D.U.T. ȍ '87 Nȍ 9* PW Nȍ Nȍ 3: $0Y AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B S VD L=100μH 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 9%5'66 WRQ 9' WGRQ WRII WU WGRII   ,'0  9'' $0Y 8/16   ,' 9'' WI 9*6  DocID027319 Rev 1  9'6  $0Y STL13N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027319 Rev 1 9/16 16 Package mechanical data STL13N65M2 Figure 20. PowerFLAT™ 5x6 HV drawing 8368143_Rev_B 10/16 DocID027319 Rev 1 STL13N65M2 Package mechanical data Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_B_footprint DocID027319 Rev 1 11/16 16 Package mechanical data STL13N65M2 Table 9. PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 3.10 3.20 3.30 e 12/16 Max. 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 DocID027319 Rev 1 STL13N65M2 Packaging mechanical data Figure 22. PowerFLAT™ 5x6 tape(a) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) R F(5.50±0.1)(III) C L EF D1 Ø1.5 MIN. Bo (5.30±0.1) 5 Packaging mechanical data REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape. Pin 1 identification a. All dimensions are in millimeters. DocID027319 Rev 1 13/16 16 Packaging mechanical data STL13N65M2 Figure 24. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C 14/16 DocID027319 Rev 1 STL13N65M2 6 Revision history Revision history Table 10. Document revision history Date Revision 18-Dec-2014 1 Changes First release. DocID027319 Rev 1 15/16 16 STL13N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 16/16 DocID027319 Rev 1