STL15N60M2-EP

STL15N60M2-EP N-channel 600 V, 0.389 Ω typ., 7 A MDmesh™ M2 EP Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max. ID PTOT STL15N60M2-EP 650 V 0.418 Ω 7A 55 W 1 2 • • • • • 3 4 PowerFLAT™ 5x6 HV Applications Figure 1: Internal schematic diagram D(5, 6, 7, 8) 8 7 6 Extremely low gate charge Excellent output capacitance (COSS) profile Very low turn-off switching losses 100% avalanche tested Zener-protected 5 • • Switching applications Tailored for very high frequency converters (f > 150 kHz) Description G(4) 1 S(1, 2, 3) 2 3 4 Top View This device is an N-channel Power MOSFET developed using MDmesh™ M2 EP enhanced performance technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics with very low turn-off switching losses, rendering it suitable for the most demanding very high frequency converters. AM15540v1 Table 1: Device summary Order code Marking Package Packing STL15N60M2-EP 15N60M2EP PowerFLAT™ 5x6 HV Tape and reel June 2015 DocID027974 Rev 1 This is information on a product in full production. 1/16 www.st.com Contents STL15N60M2-EP Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 PowerFLAT™ 5x6 HV package information .................................... 11 4.2 PowerFLAT™ 5x6 packing information ........................................... 13 Revision history ............................................................................ 15 DocID027974 Rev 1 STL15N60M2-EP 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 7 Drain current (continuous) at Tcase = 100 °C 4.6 IDM Drain current (pulsed) 28 A PTOT Total dissipation at Tcase = 25 °C 55 W (2) IAR Avalanche current, repetitive or not repetitive 1.5 A (3) EAS mJ ID (1) Single pulse avalanche energy 110 dv/dt (4) Peak diode recovery voltage slope 15 dv/dt (5) MOSFET dv/dt ruggedness 50 Tstg Storage temperature Tj Operating junction temperature A V/ns -55 to 150 °C Value Unit Notes: (1) (2) (3) Pulse width is limited by safe operating area. Pulse width limited by Tjmax. starting Tj = 25 °C, ID = IAR, VDD = 50 V. (4) ISD ≤ 7 A, di/dt=400 A/μs; VDS peak < V(BR)DSS, VDD = 80% V(BR)DSS. (5) VDS ≤ 480 V. Table 3: Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case Thermal resistance junction-ambient 2.27 59 °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. DocID027974 Rev 1 3/16 Electrical characteristics 2 STL15N60M2-EP Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C 100 ±10 µA 3 4 V 0.389 0.418 Ω Min. Typ. Max. Unit - 590 - - 30 - - 1.1 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4.5 A 2 µA Table 5: Dynamic Symbo l Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 148 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 7 - Ω Qg Total gate charge - 17 - Qgs Gate-source charge - 3.1 - Qgd Gate-drain charge VDD = 480 V, ID = 11 A, VGS = 10 V (see Figure 16: "Gate charge test circuit") - 7.3 - Min. Typ. Max. VDD = 400 V, ID = 1.5 A, RG = 4.7 Ω, VGS = 10 V – 5 - VDD = 400 V, ID = 3.5 A, RG = 4.7 Ω, VGS = 10 V – 5.2 - Min. Typ. Max. VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Table 6: Switching energy Symbol Parameter Test conditions EOFF Turn-off energy (from 90% VGS to 0% ID) Unit µJ Table 7: Switching times Symbol td(on) tr td(off) tf 4/16 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 5.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 15: "Switching times test circuit for resistive load" and Figure 20: "Switching time waveform") DocID027974 Rev 1 - 11 - - 10 - - 40 - - 15 - Unit ns STL15N60M2-EP Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7 A (1) Source-drain current (pulsed) - 28 A (2) Forward on voltage VGS = 0 V, ISD = 7 A - 1.6 V trr Reverse recovery time - 280 ns Qrr Reverse recovery charge - 2.7 µC IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 19.5 A - 400 ns - 3.8 µC - 19 A ISDM VSD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027974 Rev 1 5/16 Electrical characteristics 2.1 6/16 STL15N60M2-EP Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027974 Rev 1 STL15N60M2-EP Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Turn-off switching loss vs drain current DocID027974 Rev 1 7/16 Electrical characteristics STL15N60M2-EP Figure 14: Source-drain diode forward characteristics 8/16 DocID027974 Rev 1 STL15N60M2-EP 3 Test circuits Test circuits Figure 15: Switching times test circuit for resistive load Figure 16: Gate charge test circuit Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID027974 Rev 1 9/16 Package information 4 STL15N60M2-EP Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 10/16 DocID027974 Rev 1 STL15N60M2-EP PowerFLAT™ 5x6 HV package information Figure 21: PowerFLAT™ 5x6 HV package outline b (x8) BOTTOM VIEW K L e Resin protrusion D2 A E2 PIN #1 ID A2 A1 SEATING PLANE SIDE VIEW D E 4.1 Package information Resin protrusion TOP VIEW 8368143_Rev_B DocID027974 Rev 1 11/16 Package information STL15N60M2-EP Table 9: PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 3.10 3.20 3.30 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 22: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 0.5 0.73 3.04 1.9 6.4 3.77 5.4 0.77 4.31 8368143_Rev_B_footprint 12/16 DocID027974 Rev 1 STL15N60M2-EP PowerFLAT™ 5x6 packing information Figure 23: PowerFLAT™ 5x6 tape outline (dimensions are in mm) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) R F(5.50±0.1)(III) C L EF D1 Ø1.5 MIN. Bo (5.30±0.1) 4.2 Package information REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs 8234350_Tape_rev_C Figure 24: PowerFLAT™ 5x6 package orientation in carrier tape DocID027974 Rev 1 13/16 Package information STL15N60M2-EP Figure 25: PowerFLAT™ 5x6 reel outline 14/16 DocID027974 Rev 1 STL15N60M2-EP 5 Revision history Revision history Table 10: Document revision history Date Revision 15-Jun-2015 1 DocID027974 Rev 1 Changes First release. 15/16 STL15N60M2-EP IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 16/16 DocID027974 Rev 1