STL15N65M5

STL15N65M5 N-channel 650 V, 0.335 Ω typ., 10 A MDmesh™ M5 Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet - production data Features Order code V DS @ TJ max. RDS(on) max ID STL15N65M5 710 V 0.375 Ω 10 A     1 2 3 4 PowerFLAT™ 5x6 HV Extremely low RDS(on) Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications Figure 1: Internal schematic diagram  Switching applications Description This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the wellknown PowerMESH™ horizontal layout. The resulting product offers extremely low onresistance, making it particularly suitable for applications requiring high power and superior efficiency. Table 1: Device summary Order code Marking Package Packing STL15N65M5 15N65M5 PowerFLAT™ 5x6 HV Tape and reel December 2016 DocID023633 Rev 2 This is information on a product in full production. 1/16 www.st.com Contents STL15N65M5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 5 2/16 4.1 Power Flat™ 5x6 HV package information ..................................... 11 4.2 Power Flat™ 5x6 HV packing information ....................................... 13 Revision history ............................................................................ 15 DocID023633 Rev 2 STL15N65M5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 5 A Drain current (pulsed) 40 A Total dissipation at TC = 25 °C 52 W IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 2.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 160 mJ Peak diode recovery voltage slope 15 V/ns IDM (1) PTOT dv/dt (2) Tstg Storage temperature range Tj Operating junction temperature range - 55 to 150 °C °C Notes: (1)Pulse (2)I SD width limited by safe operating area. ≤ 10 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD = 400 V. Table 3: Thermal data Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.4 °C/W Thermal resistance junction-pcb 59 °C/W Notes: (1)When mounted on 1inch² FR-4 board, 2 oz Cu. DocID023633 Rev 2 3/16 Electrical characteristics 2 STL15N65M5 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. 650 Zero gate voltage drain current IGSS Gate-body leakage current VGS = ± 25 V, VDS = 0 VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 5 A Unit V VDS = 650 V IDSS Max. 1 µA 100 µA ± 100 nA 4 5 V 0.335 0.375 Ω Min. Typ. Max. Unit - 816 - pF - 23 - pF - 2.6 - pF - 70 - pF - 21 - pF VDS = 650 V, TC=125 °C (1), VGS = 0 V 3 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related RG Intrinsic gate resistance f = 1 MHz open drain - 5 - Ω Qg Total gate charge - 22 - nC Qgs Gate-source charge - 5.5 - nC Qgd Gate-drain charge VDD = 520 V, ID = 5.5 A, VGS = 10 V (see Figure 16: "Test circuit for gate charge behavior") - 11 - nC VDS = 0 to 520 V, VGS = 0 V Notes: (1)C oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80 % VDSS. (2)C oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80 % VDSS. 4/16 DocID023633 Rev 2 STL15N65M5 Electrical characteristics Table 6: Switching times Symbol Parameter td(V) Voltage delay time tr(V) Voltage rise time tf(I) Current fall time tc(off) Test conditions VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times" and Figure 20: "Switching time waveform") Crossing time Min. Typ. Max Unit - 30 - ns - 8 - ns - 11 - ns - 12.5 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol Parameter Test conditions ISD Source-drain current - 10 A ISDM(1) Source-drain current (pulsed) - 40 A VSD(2) Forward on voltage ISD = 10 A, VGS = 0 - 1.5 V trr Reverse recovery time - 244 ns Qrr Reverse recovery charge - 2.35 µC IRRM Reverse recovery current ISD = 10 A, di/dt = 100 A/µs VDD = 100 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 19.2 A ISD = 10 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 308 ns - 2.93 µC - 19 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. DocID023633 Rev 2 5/16 Electrical characteristics 2.1 6/16 STL15N65M5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Static drain-source on-resistance Figure 7: Gate charge vs gate-source voltage DocID023633 Rev 2 STL15N65M5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID023633 Rev 2 7/16 Electrical characteristics STL15N65M5 Figure 14: Switching energy vs gate resistance(1) Notes: (1)Eon 8/16 including reverse recovery of a SiC diode. DocID023633 Rev 2 STL15N65M5 3 Test circuits Test circuits Figure 16: Test circuit for gate charge behavior Figure 15: Test circuit for resistive load switching times Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform AM05540v2_for_M5 DocID023633 Rev 2 9/16 Package information 4 STL15N65M5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10/16 DocID023633 Rev 2 STL15N65M5 4.1 Package information Power Flat™ 5x6 HV package information Figure 21: PowerFLAT™ 5x6 HV package outline 8368143_Rev_3 DocID023633 Rev 2 11/16 Package information STL15N65M5 Table 8: PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.10 5.20 5.30 E 6.05 6.15 6.25 E2 3.10 3.20 3.30 D2 4.30 4.40 4.50 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 22: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_3_footprint 12/16 DocID023633 Rev 2 STL15N65M5 4.2 Package information Power Flat™ 5x6 HV packing information Figure 23: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 24: PowerFLAT™ 5x6 package orientation in carrier tape DocID023633 Rev 2 13/16 Package information STL15N65M5 Figure 25: PowerFLAT™ 5x6 reel 14/16 DocID023633 Rev 2 STL15N65M5 5 Revision history Revision history Table 9: Document revision history Date Revision 26-Jun-2013 1 First release 2 Updated title, features and description in cover page. Updated Figure 1: "Internal schematic diagram", Table 2: "Absolute maximum ratings" and Section 4: "Package information". Minor text changes. 05-Dec-2016 Changes DocID023633 Rev 2 15/16 STL15N65M5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 16/16 DocID023633 Rev 2