STL16N1VH5

STL16N1VH5 N-channel 12 V, 0.0022 Ω , 16 A, PowerFLAT™ (3.3 x 3.3) STripFET™ V Power MOSFET Features Order code VDSS RDS(on) max ID STL16N1VH5 12 V 0.003 Ω 16 A (1) ) s ( ct 1. The value is rated according Rthj-pcb u d o ■ Improved die-to-footprint ratio ■ Very low profile package (1mm max) ■ Very low thermal resistance ■ Very low gate charge ■ Very low on-resistance ■ Optimized to be driven @ 2.5 V ■ In compliance with the 2002/95/EC European directive Applications ■ r P e PowerFLAT™(3.3x3.3) ) (s t e l o s b O Figure 1. t c u Switching applications Internal schematic diagram 1 2 3 4 S S S G d o r Description P e This device is an N-channel Power MOSFET developed using STMicroelectronics’ STripFET™V technology. The device has been optimized to achieve very low on-state resistance, contributing to an FOM that is among the best in its class. t e l o bs O D D D D 8 7 6 5 BOTTOM VIEW Table 1. Device summary Order code Marking Package Packaging STL16N1VH5 16N1V PowerFLAT™ (3.3 x 3.3) Tape and reel June 2011 Doc ID 16802 Rev 2 1/14 www.st.com 14 Contents STL16N1VH5 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits .............................................. 8 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 2/14 Doc ID 16802 Rev 2 STL16N1VH5 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS = 0) 12 V VGS Gate-source voltage ±8 V ID(1) Drain current (continuous) at TC = 25 °C 16 A ID (1) Drain current (continuous) at TC=100 °C 10 A (2) Drain current (pulsed) 64 PTOT(3) Total dissipation at TC = 25 °C 50 PTOT(1) Total dissipation at TC = 25 °C du IDM 2 ro Derating factor TJ W W -55 to 150 °C Value Unit 2.5 °C/W Thermal resistance junction-pcb 42.8 °C/W Thermal resistance junction-pcb 63.5 °C/W Value Unit 2. Pulse width limited by safe operating area. 3. The value is rated according Rthj-c ) (s P e t e l o s b O Thermal resistance ct Symbol du ro (1) P e Rthj-pcb (2) Parameter Thermal resistance junction-case (drain) Rthj-case Rthj-pcb ct W/°C 1. The value is rated according to Rthj-pcb Table 3. A 0.4 Operating junction temperature storage temperature Tstg (s) t e l o 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec 2. Steady state s b O Table 4. Symbol Avalanche data Parameter IAV Not-repetitive avalanche current (pulse width limited by Tj Max) 11 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID=IAV, VDD = 12 V, L=6 mH) 350 mJ Doc ID 16802 Rev 2 3/14 Electrical characteristics 2 STL16N1VH5 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. On/off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage ID = 250 µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ± 8 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 4.5 V, ID= 8 A Dynamic Symbol Ciss Coss Crss Qg Parameter od Qgd Total gate charge Gate-source charge Gate-drain charge RG Gate input resistance r P e Qgs let t c u VGS= 2.5 V, ID= 8 A e t e ol s b O VDS = 12 V, f=1 MHz, VGS=0 Max. 12 VGS = 4.5 V Doc ID 16802 Rev 2 1 10 µA µA ±100 nA ) s ( ct u d o V Pr 0.0022 0.0032 0.003 0.004 Ω Ω Min. Typ. Max. Unit - 2085 949 240 - pF pF pF - 26.5 5.2 4.8 - nC nC nC - 1.5 - Ω (see Figure 14) f=1 MHz Gate DC Bias = 0 Test signal level = 20mV Open drain Unit V 0.5 VDD=12 V, ID = 16 A O 4/14 Typ. VDS = Max rating @125 °C Test conditions ) (s Input capacitance Output capacitance Reverse transfer capacitance Min. VDS = Max rating, IDSS Table 6. o s b Test conditions STL16N1VH5 Electrical characteristics Table 7. Switching times Symbol td(on) tr td(off) tf Table 8. Parameter Turn-on delay time Rise time Turn-off delay time Fall time Min. Typ. - 14.4 31.6 50 16 Min. Typ. VDD=6 V, ID= 8 A, RG=4.7 Ω, VGS=4.5 V (see Figure 13) Parameter Test conditions Source-drain current - ISDM(1) Source-drain current (pulsed) - VSD(2) Forward on voltage ISD=16 A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current di/dt = 100 A/µs, VDD=10 V, Tj=150 °C trr Qrr IRRM Max. Unit - ns ns ns ns Source drain diode Symbol ISD Test conditions 1. Pulse width limited by safe operating area ISD=16 A, o s b e t e l (see Figure 18) Pr u d o - - ) s ( ct 49 54 2.2 Max. Unit 16 A 64 A 1.1 V ns nC A O ) 2. Pulsed: pulse duration= 300 µs, duty cycle 1.5% s ( t c u d o r P e t e l o s b O Doc ID 16802 Rev 2 5/14 Electrical characteristics STL16N1VH5 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Thermal impedance AM09194v1 ID (A) 100 Figure 3. a is are (on) this RDS n in ax io m t era by Op ited Lim PCB_PowerFLAT K Tj=150°C Tc=25°C Single pulse -1 10 10 10ms Zth-pcb=k*Rthj-pcb, Rthj-pcb = 63.5°C/W 100ms 1 1s -2 ) s ( ct 10 0.1 Figure 4. ID (A) u d o -3 0.01 0.1 10 1 10 -3 10 VDS(V) Output characteristics -2 VGS=5V 3V 10 10 1 2 10 10 tp (s) r P e Figure 5. AM09195v1 0 -1 10 Transfer characteristics t e l o ID (A) AM09196v1 60 200 s b O VDS=2V 50 2.5V 150 t(s 100 0 0 r P e 0.5 uc od 50 1.0 1.5 2.0 2V 30 20 10 0 0 VDS(V) 2.5 Normalized BVDSS vs temperature AM09197v1 BVDSS s b O 40 1.5V t e l o Figure 6. )- (norm) Figure 7. 1 2 VGS(V) Static drain-source on resistance AM09198v1 RDS(on) (mΩ) 1.08 6 ID=250µA VGS=4.5V 1.06 5 1.04 1.02 4 1.00 3 0.98 2 0.96 1 0.94 0.92 -50 -25 6/14 0 0 25 50 75 100 125 TJ(°C) Doc ID 16802 Rev 2 0 2 4 6 8 10 12 14 16 ID(A) STL16N1VH5 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. Capacitance variations AM09199v1 VGS (V) AM09200v1 C (pF) ID=16A VDD=12V VGS=4.5V 5 3500 3000 4 2500 Ciss 2000 3 1500 2 1000 1 Coss ) s ( ct 500 0 0 10 5 15 20 25 Qg(nC) Figure 10. Normalized gate threshold voltage vs temperature (norm) 2 ID=250µA let 1.8 o s b 1.6 1.10 1.4 O ) 0.90 s ( t c 0.80 0.70 -50 -25 0 e t e ol u d o Pr 25 50 8 u d o 10 VDS(V) r P e RDS(on) (norm) 1.00 6 4 Figure 11. Normalized on resistance vs temperature AM09201v1 VGS(th) Crss 0 0 AM09202v1 ID=8A VGS=4.5V 1.2 1.0 0.8 0.6 0.4 0.2 75 100 125 150 TJ(°C) 0 -50 -25 0 25 50 75 100 125 TJ(°C) Figure 12. Source-drain diode forward characteristics s b O AM09203v1 VSD (V) TJ=-50°C 0.8 0.7 TJ=25°C 0.6 0.5 TJ=150°C 0.4 0.3 0.2 0 2 4 6 8 10 12 14 16 ISD(A) Doc ID 16802 Rev 2 7/14 Test circuits 3 STL16N1VH5 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 µF 2200 RL µF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 µF D.U.T. ) s ( t VG 2.7kΩ c u d PW 47kΩ 1kΩ PW D.U.T. AM01468v1 e t e ol o r P AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B A D G S s ( t c 3.3 µF B 25 Ω D 1000 µF RG S r P e 2200 µF 3.3 µF VDD ID Vi D.U.T. Pw let AM01470v1 Figure 17. Unclamped inductive waveform b O L VD VDD u d o G so )- L=100µH s b O AM01471v1 Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/14 0 Doc ID 16802 Rev 2 10% AM01473v1 STL16N1VH5 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 16802 Rev 2 9/14 Package mechanical data Table 9. STL16N1VH5 PowerFLAT™ (3.3 x 3.3) package dimensions mm. Dim. Min. Typ Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.25 0.30 0.35 D 3.30 D2 2.50 2.65 e 0.65 E 3.30 E2 1.76 1.91 L 0.30 0.40 e t e ol ) (s s b O t c u d o r P e t e l o s b O 10/14 Doc ID 16802 Rev 2 2.75 ) s ( ct o r P du 2.01 0.50 STL16N1VH5 Package mechanical data Figure 19. PowerFLAT™ (3.3 x 3.3) package drawing ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 8072823_E Doc ID 16802 Rev 2 11/14 Package mechanical data STL16N1VH5 Figure 20. Recommended footprint (dimensions in mm) ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 12/14 Doc ID 16802 Rev 2 STL16N1VH5 5 Revision history Revision history Table 10. Document revision history Date Revision Changes 20-Nov-2009 1 First release. 21-Jun-2011 2 Document status promoted from preliminary data to datasheet. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Doc ID 16802 Rev 2 13/14 STL16N1VH5 ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. 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