STL16N65M2

STL16N65M2 N-channel 650 V, 0.325 Ω typ., 7.5 A MDmesh M2 Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet − production data Features Order code VDS @ TJmax RDS(on) max ID STL16N65M2 710 V 0.395 Ω 7.5 A • Extremely low gate charge 1 2 3 • Excellent output capacitance (Coss) profile • 100% avalanche tested 4 • Zener-protected PowerFLAT™ 5x6 HV Applications • Switching applications Figure 1. Internal schematic diagram D(5, 6, 7, 8) Description 8 7 6 5 1 2 3 4 G(4) S(1, 2, 3) This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Top View AM15540v2 Table 1. Device summary Order codes Marking Package Packaging STL16N65M2 16N65M2 PowerFLAT™ 5x6 HV Tape and reel October 2014 This is information on a product in full production. DocID027128 Rev 1 1/16 www.st.com Contents STL16N65M2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 .............................................. 8 DocID027128 Rev 1 STL16N65M2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Value Unit Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 7.5 A ID Drain current (continuous) at TC = 100 °C 4.7 A IDM (1) Drain current (pulsed) 30 A PTOT VGS Parameter Total dissipation at TC = 25 °C 56 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C Value Unit Tstg Tj Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area. 2. ISD ≤ 7.5 A, di/dt ≤ 400 A/µs; V DS peak < V(BR)DSS, VDD=400 V. 3. VDS ≤ 520 V Table 3. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case max 2.23 °C/W Rthj-pcb Thermal resistance junction-pcb max(1) 59 °C/W Value Unit 1. When mounted on 1 inch² FR-4, 2 Oz copper board Table 4. Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.5 A EAS Single pulse avalanche energy (starting Tj=25°C, ID= IAR; VDD=50) 115 mJ DocID027128 Rev 1 3/16 16 Electrical characteristics 2 STL16N65M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 650 V VGS = 0, VDS = 650 V 1 µA VGS = 0, VDS = 650 V, TC=125 °C 100 µA VDS = 0, VGS = ± 25 V ±10 µA 3 4 V 0.325 0.395 Ω Min. Typ. Max. Unit - 718 - pF - 32 - pF - 1.1 - pF VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance 2 VGS = 10 V, ID = 3.5 A Table 6. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VGS = 0, VDS = 0 to 520 V - 189 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 5.2 - Ω Qg Total gate charge - 19.5 - nC - 4 - nC - 8.3 - nC Qgs Gate-source charge Qgd Gate-drain charge VGS = 0, VDS = 100 V, f = 1 MHz VDD = 520 V, ID = 11 A, VGS = 10 V (see Figure 15) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/16 DocID027128 Rev 1 STL16N65M2 Electrical characteristics Table 7. Switching times Symbol td(on) Parameter Test conditions td(off) tf Typ. Max. Unit - 11.3 - ns - 8.2 - ns - 36 - ns - 11.3 - ns Turn-on delay time VDD = 325 V, ID = 5.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14 and 19) Rise time tr Min. Turn-off delay time Fall time Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7.5 A ISDM (1) Source-drain current (pulsed) - 30 A VSD (2) Forward on voltage - 1.6 V ISD trr VGS = 0, ISD = 11 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/µs VDD = 60 V (see Figure 16) ISD = 11 A, di/dt = 100 A/µs VDD = 60 V, Tj=150 °C (see Figure 16) - 342 ns - 3.5 µC - 20.4 A - 458 ns - 4.6 µC - 20.5 A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027128 Rev 1 5/16 16 Electrical characteristics 2.1 STL16N65M2 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance *,3')65 ,' $ H DU 0.2  RQ —V  LV '6 WK 5 LQ D[  Q P WLR \ UD GE SH WH 2 LPL /  δ=0.5 LV D  ZthPowerFlat_5x6_19 K 0.1 10 -1 0.05 0.02 0.01 —V PV PV 10 -2 Single pulse  7M ƒ& 7F ƒ& 6LQJOHSXOVH     9'69  Figure 4. Output characteristics *,3')65 ,' $ 9*6 9  10-3 10 -2 10 -1 100 tp(s) *,3')65 ,' $    9 9'6 9      9   9'69  Figure 6. Normalized gate threshold voltage vs. temperature GIPD180920141442FSR VGS(th) (norm) ID = 250 µA 1.1   1.08 0.9 1.00 0.8 0.96 0.7 0.92 25 75 125 Tj(°C)    9*69 GIPD180920141448FSR V(BR)DSS (norm) 1.04 -25  Figure 7. Normalized V(BR)DSS vs. temperature 1.0 0.6 -75 10-4 Figure 5. Transfer characteristics    10-5  9  6/16 10 -3 10-6 0.88 -75 DocID027128 Rev 1 ID= 1mA -25 25 75 125 Tj(°C) STL16N65M2 Electrical characteristics Figure 8. Static drain-source on-resistance *,3')65 5'6RQ ȍ 9*6 9 Figure 9. Normalized on-resistance vs. temperature  2.2  1.8  1.4  1  0.6         ,'$ Figure 10. Gate charge vs. gate-source voltage *,3')65 9'6 9 9*6 9 9'6 9'' 9 ,' $         GIPD180920141459FSR RDS(on) (norm) VGS= 10V 0.2 -75 -25 75 25 125 Tj(°C) Figure 11. Capacitance variations *,3')65 & S) &LVV   &RVV  &UVV           4JQ& Figure 12. Output capacitance stored energy *,3')65 ( —-      Figure 13. Source-drain diode forward characteristics *,3')65 96' 9   9'69  7M ƒ&    7M ƒ&      7M ƒ&          9'69  DocID027128 Rev 1       ,6'$ 7/16 16 Test circuits 3 STL16N65M2 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 16. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 17. Unclamped inductive load test circuit L A D G D.U.T. FAST DIODE B B VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton 9%5'66 tdon 9' toff tr tdoff tf 90% 90% ,'0 10% ,' 9'' 10% 0 9'' VDS 90% VGS $0Y 8/16 0 DocID027128 Rev 1 10% AM01473v1 STL16N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027128 Rev 1 9/16 16 Package mechanical data STL16N65M2 Figure 20. PowerFLAT™ 5x6 HV drawing 8368143_Rev_B 10/16 DocID027128 Rev 1 STL16N65M2 Package mechanical data Table 9. PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 3.10 3.20 3.30 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 DocID027128 Rev 1 11/16 16 Package mechanical data STL16N65M2 Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_B_footprint 12/16 DocID027128 Rev 1 STL16N65M2 Packaging mechanical data Figure 22. PowerFLAT™ 5x6 tape(a) P0 4.0±0.1 (II) P2 2.0±0.1 (I) T (0.30 ±0.05) E1 1.75±0.1 Y 0. 20 Do Ø1.55±0.05 W(12.00±0.3) R F(5.50±0.1)(III) C L EF D1 Ø1.5 MIN. Bo (5.30±0.1) 5 Packaging mechanical data REF .R0 .50 Y P1(8.00±0.1) Ao(6.30±0.1) Ko (1.20±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs (II) Cumulative tolerance of 10 sprocket holes is ± 0.20 . (III) Measured from centerline of sprocket hole to centerline of pocket. 8234350_Tape_rev_C Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape. Pin 1 identification a. All dimensions are in millimeters. DocID027128 Rev 1 13/16 16 Packaging mechanical data STL16N65M2 Figure 24. PowerFLAT™ 5x6 reel R0.60 W3 11.9/15.4 PART NO. 1.90 2.50 R25.00 ØN 178(±2.0) ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES W2 18.4 (max) A 330 (+0/-4.0) 4.00 2.50 77 ESD LOGO W1 12.4 (+2/-0) 06 PS ØA 128 2.20 R1.10 Ø21.2 All dimensions are in millimeters 13.00 CORE DETAIL 8234350_Reel_rev_C 14/16 DocID027128 Rev 1 STL16N65M2 6 Revision history Revision history Table 10. Document revision history Date Revision 31-Oct-2014 1 Changes First release. DocID027128 Rev 1 15/16 16 STL16N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 16/16 DocID027128 Rev 1