STL17N60M6

STL17N60M6 Datasheet N-channel 600 V, 300 mΩ typ., 10 A, MDmesh™ M6 Power MOSFET in a PowerFLAT™ 8x8 HV package Features 5 4 3 2 1 PowerFLAT™ 8x8 HV Drain(5) Order code VDS RDS(on) max. ID STL17N60M6 600 V 350 mΩ 10 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • Gate(1) Driver source (2) Power source (3, 4) NG1DS2PS34D5Z Switching applications LLC converters Boost PFC converters Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STL17N60M6 Product summary Order code STL17N60M6 Marking 17N60M6 Package PowerFLAT™ 8x8 HV Packing Tape and reel DS12921 - Rev 1 - February 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL17N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 10 Drain current (continuous) at Tcase = 100 °C 6.3 IDM(1) Drain current (pulsed) 32 A PTOT Total power dissipation at Tcase = 25 °C 90 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 100 Tstg Storage temperature range VGS ID Tj Parameter A V/ns -55 to 150 °C Value Unit Thermal resistance junction-case 1.4 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit 2.5 A 110 mJ Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 10 A, di/dt ≤ 400 A/μs, VDS(peak) < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on 1 inch2 FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR EAS DS12921 - Rev 1 Parameter Avalanche current, repetitive or non-repetitive (pulse width limited by TJmax) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) page 2/15 STL17N60M6 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified). Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current IGSS 1 VGS = 0 V, VDS = 600 V, Tcase = 125 100 °C(1) Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance ID = 6 A, VGS = 10 V Unit V VGS = 0 V, VDS = 600 V IDSS Max. µA ±5 µA 4 4.75 V 300 350 mΩ Min. Typ. Max. Unit - 575 - - 33 - - 3 - 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 104 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.2 - Ω Qg Total gate charge VDD = 480 V, ID = 12 A, - 16.7 - Qgs Gate-source charge VGS = 0 to 10 V - 3.5 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 9.4 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12921 - Rev 1 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 6 A, - 13 - Rise time RG = 4.7 Ω, VGS = 10 V - 7.6 - Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 19.8 - - 6.8 - Fall time Unit ns page 3/15 STL17N60M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 8 A Source-drain current (pulsed) - 32 A 1.6 V Forward on voltage ISD = 8 A, VGS = 0 V - trr Reverse recovery time ISD = 12 A, di/dt = 100 A/µs, - 210 ns Qrr Reverse recovery charge VDD = 60 V - 1.7 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 13.8 A - 290 ns - 2.9 µC - 20 A VSD IRRM trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS12921 - Rev 1 page 4/15 STL17N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GADG120220191103SOA Zth PowerFLAT 8x8 HV K δ=0.5 tp = 1 μs Operation in this area is limited by RDS(on) 101 0.2 0.1 tp = 10 μs -1 10 0.05 tp = 100 μs 0.02 100 Zth= K*R thJ-c δ= t p/Ƭ 0.01 tp = 1 ms Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V Single pulse tp = 10 ms 10-1 10-1 100 101 VDS (V) 102 tp -2 10 -5 10 Figure 3. Output characteristics ID (A) VDS = 17 V 25 8V 20 15 15 7V 10 10 5 5 6V 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VDS (V) GIPG230320171212QVG VGS (V) VDD = 480 V, ID = 12 A 600 12 VDS 8 300 6 200 4 2 100 0 0 0 4 5 6 7 8 9 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (mΩ) GADG120220191104RID 320 10 400 DS12921 - Rev 1 GADG230320171151TCH 30 20 500 tp (s) 10 10 ID (A) VGS = 9, 10 V 25 10 Ƭ -2 -3 Figure 4. Transfer characteristics GADG230320171114OCH 30 -4 4 8 12 16 0 Qg (nC) 310 VGS = 10 V 300 290 280 0 2 4 6 8 10 12 ID (A) page 5/15 STL17N60M6 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG230320171219CVR VGS(th) (norm.) CISS 102 1 0.9 COSS f = 1 MHz CRSS 100 10-1 100 101 VDS (V) 102 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GADG230320171338RON VGS = 10 V 2.2 0.8 0.7 0.6 -75 1 1 0.96 0.6 0.92 75 125 Tj (°C) Figure 11. Output capacitance stored energy EOSS (µJ) GADG230320171345EOS 75 125 Tj (°C) GADG010220171212BDV I D = 1 mA 1.08 1.4 25 25 V (BR)DSS (norm.) 1.04 -25 -25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 ID = 250 µA 1.1 103 101 GADG230320171335VTH 0.88 -75 -25 25 75 125 T j (°C) Figure 12. Source-drain diode forward characteristics VSD (V) 6 1.1 5 1.0 4 0.9 3 0.8 2 0.7 1 0.6 GADG120220191104SDF TJ = -50 °C TJ = 25 °C TJ = 150 °C 0 0 DS12921 - Rev 1 100 200 300 400 500 600 VDS (V) 0.5 0 2 4 6 8 10 12 ISD (A) page 6/15 STL17N60M6 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD 12V 47kΩ 1kΩ 100nF + VD VGS 3.3 µF 2200 RL µF IG=CONST VDD 2200 µF + RG 100Ω Vi ≤ VGS D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ GND1 (driver signal) GND2 (power) 1kΩ PW GND1 AM15855v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE S A L L=100µH D 25Ω VD 3.3 µF B B B AM15856v1 Figure 16. Unclamped inductive load test circuit D G GND2 + 1000 µF 2200 µF + VDD 3.3 µF VDD ID G S RG D.U.T. Vi Pw GND2 GND1 D.U.T. GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform ton Figure 17. Unclamped inductive waveform td(on) toff td(off) tr tf V(BR)DSS VD 90% 90% IDM ID VDD 10% 0 VDS 10% VDD VGS 90% AM01472v1 0 10% AM01473v1 DS12921 - Rev 1 page 7/15 STL17N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12921 - Rev 1 page 8/15 STL17N60M6 PowerFLAT™ 8x8 HV package information 4.1 PowerFLAT™ 8x8 HV package information Figure 19. PowerFLAT™ 8x8 HV package outline 8222871_Rev_4 DS12921 - Rev 1 page 9/15 STL17N60M6 PowerFLAT™ 8x8 HV package information Table 8. PowerFLAT™ 8x8 HV mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 20. PowerFLAT™ 8x8 HV footprint 8222871_REV_4_footprint Note: DS12921 - Rev 1 All dimensions are in millimeters. page 10/15 STL17N60M6 PowerFLAT™ 8x8 HV packing information 4.2 PowerFLAT™ 8x8 HV packing information Figure 21. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape DS12921 - Rev 1 page 11/15 STL17N60M6 PowerFLAT™ 8x8 HV packing information Figure 23. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA Note: DS12921 - Rev 1 All dimensions are in millimeters. page 12/15 STL17N60M6 Revision history Table 9. Document revision history DS12921 - Rev 1 Date Version 14-Feb-2019 1 Changes First release. page 13/15 STL17N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT™ 8x8 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12921 - Rev 1 page 14/15 STL17N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12921 - Rev 1 page 15/15