STL180N6F7

STL180N6F7 Datasheet N-channel 60 V, 1.9 mΩ typ., 120 A, STripFET™ F7 Power MOSFET in a PowerFLAT™ 5x6 package Features D(5, 6, 7, 8) 8 7 5 6 Order code VDS RDS(on) max. ID STL180N6F7 60 V 2.4 mΩ 120 A • Among the lowest RDS(on) on the market • • Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity • High avalanche ruggedness Applications • Switching applications Description G(4) 1 2 3 4 This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Top View S(1, 2, 3) AM15540v2 Product status link STL180N6F7 Product summary Order code STL180N6F7 Marking 180N6F7 Package PowerFLAT™ 5x6 Packing Tape and reel DS12377 - Rev 2 - December 2018 For further information contact your local STMicroelectronics sales office. www.st.com STL180N6F7 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V Drain current (continuous) at TC = 25 °C 120 A Drain current (continuous) at TC = 100 °C 120 A Drain current (pulsed) 480 A Drain current (continuous) at Tpcb = 25 °C 32 A Drain current (continuous) at Tpcb = 100 °C 20 A Drain current (pulsed) 128 A PTOT(1) Total power dissipation at TC = 25 °C 166 W PTOT(3) Total power dissipation at Tpcb = 25 °C 4.8 W Tj Operating junction temperature range -55 to 175 °C Value Unit ID(1) IDM (1)(2) ID(3) IDM (2)(3) Tstg Storage temperature range 1. This value is rated according to Rthj-c and limited by package. 2. Pulse width limited by safe operating area. 3. This value is rated according to Rthj-pcb. Table 2. Thermal data Symbol Parameter Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W Rthj-case Thermal resistance junction-case 0.9 °C/W 1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s. DS12377 - Rev 2 page 2/14 STL180N6F7 Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V 1 µA IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 16 A 1.9 2.4 mΩ Min. Typ. Max. Unit - 4825 - pF - 2240 - pF - 216 - pF 60 V 2 Table 4. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge VDD = 30 V, ID = 32 A, - 79.5 - nC Qgs Gate-source charge VGS = 0 to 10 V - 24.2 - nC Gate-drain charge (see Figure 13. Test circuit for gate charge behavior) - 24.1 - nC Min. Typ. Max. Unit Qgd VDS = 25 V, f = 1 MHz, VGS = 0 V Table 5. Switching times Symbol td(on) tr td(off) tf Parameter Test conditions Turn-on delay time VDD = 30 V, ID = 16 A, - 33.9 - ns Rise time RG = 4.7 Ω, VGS = 10 V - 35.6 - ns Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 68.9 - ns - 42.2 - ns Min. Typ. Max. Unit 1.2 V Fall time Table 6. Source-drain diode Symbol VSD (1) trr Qrr IRRM Parameter Test conditions Forward on voltage ISD = 32 A, VGS = 0 V - Reverse recovery time ID = 32 A, di/dt = 100 A/µs - 60.3 ns Reverse recovery charge VDD = 48 V - 72.4 nC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 2.4 A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS12377 - Rev 2 page 3/14 STL180N6F7 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance K GADG101220181412SOA GADG101220181413ZTH δ = 0.5 Operation in this area is limited by RDS(on) 102 δ = 0.2 δ = 0.1 tp =100 µs 101 Single pulse tp =10 ms 10-1 10-1 100 δ = 0.02 δ = 0.01 tp =1 ms TJ ≤ 175 °C TC = 25 °C single pulse 100 VDS (V) 101 10 -2 10 -5 Figure 3. Output characteristics ID (A) δ = 0.05 10 -1 GADG101220181450OCH VGS = 8, 9, 10 V 10 -3 ID (A) 360 GADG101220181413TCH VDS = 6 V 240 VGS = 6 V 100 200 160 TJ = 175 °C 120 50 80 VGS = 5 V 1 2 3 4 5 6 7 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) 8 GADG101220181414QVG 0 0 TJ = -55 °C TJ = 25 °C 40 10 tp (s) 10 -1 280 VGS = 7 V 0 0 10 -2 Figure 4. Transfer characteristics 320 150 10 -4 1 2 3 4 5 6 7 VGS (V) Figure 6. Static drain-source on-resistance RDS(on) (mΩ) GADG101220181415RID 1.92 VDS = 30 V, ID = 32 A 1.91 VGS = 10 V 6 1.90 4 1.89 2 1.88 0 0 DS12377 - Rev 2 20 40 60 80 100 Qg (nC) 1.87 0 5 10 15 20 25 30 ID (A) page 4/14 STL180N6F7 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG101220181414CVR VGS(th) (norm.) GADG101220181415VTH 1.1 104 103 CISS 1.0 COSS 0.9 ID = 250 µA 0.8 102 0.7 CRSS 101 10-1 100 0.6 0.5 -75 VDS (V) 101 25 75 125 175 Tj (°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) -25 V(BR)DSS (norm.) GADG101220181416RON GADG101220181415BDV 1.8 1.04 1.6 VGS = 10 V ID = 16 A 1.4 ID = 10 mA 1.02 1.2 1.00 1.0 0.98 0.8 0.6 -75 -25 25 75 125 175 0.96 -75 Tj (°C) -25 25 75 125 175 Tj (°C) Figure 11. Source-drain diode forward characteristics VSD (V) GADG101220181416SDF TJ = -55 °C 0.9 0.8 TJ = 25 °C 0.7 0.6 0.5 TJ = 175 °C 0.4 0.3 0 DS12377 - Rev 2 5 10 15 20 25 30 ISD (A) page 5/14 STL180N6F7 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12377 - Rev 2 page 6/14 STL180N6F7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12377 - Rev 2 page 7/14 STL180N6F7 PowerFLAT™ 5x6 type C package information 4.1 PowerFLAT™ 5x6 type C package information Figure 18. PowerFLAT™ 5x6 type C package outline Bottom view Side view Top view 8231817_typeC_A0ER_Rev17 DS12377 - Rev 2 page 8/14 STL180N6F7 PowerFLAT™ 5x6 type C package information Table 7. PowerFLAT™ 5x6 type C package mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 D3 4.05 4.20 4.35 D4 4.80 5.00 5.20 D5 0.25 0.40 0.55 D6 0.15 0.30 0.45 e 0.50 4.45 1.27 E 5.95 6.15 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.75 0.90 1.05 K 1.05 1.35 L 0.725 1.025 L1 0.05 θ 0° 0.15 6.35 0.25 12° Figure 19. PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_simp_Rev_17 DS12377 - Rev 2 page 9/14 STL180N6F7 PowerFLAT™ 5x6 packing information 4.2 PowerFLAT™ 5x6 packing information Figure 20. PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 21. PowerFLAT™ 5x6 package orientation in carrier tape Pin 1 identification DS12377 - Rev 2 page 10/14 STL180N6F7 PowerFLAT™ 5x6 packing information Figure 22. PowerFLAT™ 5x6 reel DS12377 - Rev 2 page 11/14 STL180N6F7 Revision history Table 8. Document revision history Date Revision 15-Nov-2017 1 Changes Initial release Removed maturity status indication from cover page. 12-Dec-2018 2 Updated Section 2 Electrical characteristics and Section 4 Package information. Added Section 2.1 Electrical characteristics (curves). Minor text changes DS12377 - Rev 2 page 12/14 STL180N6F7 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4.1 PowerFLAT 5x6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS12377 - Rev 2 page 13/14 STL180N6F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12377 - Rev 2 page 14/14