STL18N60M2

STL18N60M2 N-channel 600 V, 0.278 Ω typ., 9 A MDmesh™ M2 Power MOSFET in a PowerFLAT™ 5x6 HV package Datasheet - production data Features Order code VDS @ TJmax RDS(on) max. ID STL18N60M2 650 V 0.308 Ω 9A     1 2 3 4 Applications PowerFLAT™ 5x6 HV  8 7 6 5 1 2 3 4 G(4) S(1, 2, 3) Switching applications Description Figure 1: Internal schematic diagram D(5, 6, 7, 8) Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Top View Table 1: Device summary Order code Marking Package Packing STL18N60M2 18N60M2 PowerFLAT™ 5x6 HV Tape and reel August 2017 DocID026517 Rev 2 This is information on a product in full production. 1/15 www.st.com Contents STL18N60M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 5x6 HV package information .................................... 10 4.2 PowerFLAT™ 5x6 packing information ........................................... 12 Revision history ............................................................................ 14 DocID026517 Rev 2 STL18N60M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 25 V ID(1) Drain current (continuous) at TC = 25 °C 9 A ID(1) Drain current (continuous) at TC= 100 °C 5.5 A IDM(2) Drain current (pulsed) 36 A Total dissipation at TC = 25 °C 57 W IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 2 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 135 mJ dv/dt(3) Peak diode recovery voltage slope 15 V/ns dv/dt(4) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range - 55 to 150 °C Value Unit PTOT (2) Tj Operating junction temperature range Notes: (1)The value is limited by package. (2)Pulse (3)I SD (4)V width limited by safe operating area. ≤ 9 A, di/dt ≤ 400 A/µs; VDS(peak) ≤ V(BR)DSS, VDD = 400 V. DS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.2 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 59 °C/W Notes: (1)When mounted on 1inch2 FR-4 board, 2 oz Cu. DocID026517 Rev 2 3/15 Electrical characteristics 2 STL18N60M2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA VGS = 0 V, VDS = 600 V, TC = 125 °C (1) 100 µA Gate-body leakage current VDS = 0 V, VGS = ±25 V 10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4.5 A 0.278 0.308 Ω Min. Typ. Max. Unit - 791 - pF - 40 - pF 1.3 - pF IDSS Zero gate voltage drain current IGSS 2 Notes: (1) Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Output equivalent capacitance VDS = 0 V to 480 V, VGS = 0 V - 164.5 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.6 - Ω VDD = 480 V, ID = 13 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior") - 21.5 - nC - 3.2 - nC - 11.3 - nC Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80 % VDS. Table 6: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 300 V, ID = 6.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") DocID026517 Rev 2 Min. Typ. Max. Unit - 12 - ns - 9 - ns - 47 - ns - 10.6 - ns STL18N60M2 Electrical characteristics Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 9 A ISDM(1) Source-drain current (pulsed) - 36 A VSD(2) Forward on voltage VGS = 0 V, ISD = 13 A - 1.6 V trr Reverse recovery time - 305 ns Qrr Reverse recovery charge - 3.3 µC IRRM Reverse recovery current ISD = 13 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 22 A ISD = 13 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 417 ns - 4.6 µC - 22.2 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse (2) width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5 %. DocID026517 Rev 2 5/15 Electrical characteristics 2.1 STL18N60M2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K ZthPowerFlat_5x6_19 d=0.5 0.2 10-1 0.1 10-2 10-3 -6 10 0.05 0.02 0.01 Single pulse 10-5 10-4 10-3 10-2 10-1 100 tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID026517 Rev 2 STL18N60M2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Source-drain diode forward characteristics DocID026517 Rev 2 7/15 Test circuits 3 8/15 STL18N60M2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID026517 Rev 2 STL18N60M2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026517 Rev 2 9/15 Package information 4.1 STL18N60M2 PowerFLAT™ 5x6 HV package information C Figure 20: PowerFLAT™ 5x6 HV package outline 8368143_Rev_4 10/15 DocID026517 Rev 2 STL18N60M2 Package information Table 8: PowerFLAT™ 5x6 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.8 6 6.1 D 5.10 5.20 5.30 E 6.05 6.15 6.25 E2 3.10 3.20 3.30 D2 4.30 4.40 4.50 D4 4.8 5 5.1 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 21: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_3_footprint DocID026517 Rev 2 11/15 Package information 4.2 STL18N60M2 PowerFLAT™ 5x6 packing information Figure 22: PowerFLAT™ 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_ Tape_rev_C Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID026517 Rev 2 STL18N60M2 Package information Figure 24: PowerFLAT™ 5x6 reel DocID026517 Rev 2 13/15 Revision history 5 STL18N60M2 Revision history Table 9: Document revision history Date Revision 12-Jun-2014 1 First release. 2 Updated title, features and description in cover page. Updated Table 4: "On/off states", Figure 3: "Thermal impedance", Figure 11: "Normalized on-resistance vs temperature" and Section 4: "Package information". Minor text changes. 02-Aug-2017 14/15 Changes DocID026517 Rev 2 STL18N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID026517 Rev 2 15/15