STL18N65M2

STL18N65M2 Datasheet N-channel 650 V, 0.290 Ω typ., 8 A MDmesh M2 Power MOSFET in a PowerFLAT 5x6 HV package Features 1 2 3 4 PowerFLAT 5x6 HV D(5, 6, 7, 8) Order code VDS @ TJmax RDS(on ) max. ID STL18N65M2 715 V 0.365 Ω 8A • • Extremely low gate charge Excellent output capacitance (Coss) profile • • 100% avalanche tested Zener-protected Applications • G(4) Switching applications Description S(1, 2, 3) AM15540v7 This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL18N65M2 Product summary Order code STL18N65M2 Marking 18N65M2 Package PowerFLAT 5x6 HV Packing Tape and reel DS10248 - Rev 4 - July 2020 For further information contact your local STMicroelectronics sales office. www.st.com STL18N65M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit ±25 V Drain current (continuous) at TC = 25 °C 8 A Drain current (continuous) at TC = 100 °C 5 A Drain current pulsed 32 A Total power dissipation at TC = 25 °C 57 W IAR Avalanche current, repetitive or non-repetitive (pulse width limited by TJ max) 1.8 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 120 mJ dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 VGS ID (1) IDM (2) PTOT TJ Tstg Parameter Gate-source voltage Operating junction temperature range V/ns -55 to 150 °C Value Unit Thermal resistance junction-case 2.2 °C/W Thermal resistance junction-ambient 59 °C/W Storage temperature range 1. The value is limited by package. 2. Pulse width is limited by safe operating area. 3. ISD ≤ 8 A, di/dt ≤ 400 A/μs, VDS(peak) ≤ V(BR)DSS, VDD = 400 V. 4. VDS ≤ 520 V. Table 2. Thermal data Symbol Rthj-case Rthj-amb (1) Parameter 1. When mounted on 1inch² FR-4 board, 2 oz Cu. DS10248 - Rev 4 page 2/15 STL18N65M2 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 650 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A VGS = 0 V, VDS = 650 V, TC = 125 °C Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1 µA 100 µA ±10 µA 3 4 V 0.290 0.365 Ω Min. Typ. Max. Unit - 770 - pF - 35 - pF - 1.2 - pF (1) 2 1. Defined by design, not subject to production test. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V Equivalent capacitance energy related VDS = 0 to 520 V, VGS = 0 V - 175 - pF Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6.1 - Ω Qg Total gate charge VDD = 520 V, ID = 12 A - 20 - nC Gate-source charge VGS = 0 to 10 V - 3.6 - nC Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 8.5 - nC Coss eq. (1) Qgs Qgd 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 5. Switching times Symbol td(on) tr td(off) tf DS10248 - Rev 4 Parameter Test conditions Min. Typ. Max. Unit Turn-on delay time VDD = 325 V, ID = 6.5 A, - 11 - ns Rise time RG = 4.7 Ω, VGS = 6 V - 7.5 - ns Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 46 - ns - 12.5 - ns Fall time page 3/15 STL18N65M2 Electrical characteristics Table 6. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 8 A ISDM (1) Source-drain current (pulsed) - 32 A VSD (2) Forward on voltage ISD = 8 A, VGS = 0 V - 1.6 V Reverse recovery time ISD = 12 A, di/dt = 100 A/µs, - 331 ns Reverse recovery charge VDD = 60 V - 3.4 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 20.5 A trr Reverse recovery time ISD = 12 A, di/dt = 100 A/µs, - 462 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 4.6 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 20 A trr Qrr IRRM 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS10248 - Rev 4 page 4/15 STL18N65M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area ID (A) GADG170720201544ZTH K GADG150720201315SOA δ =0.5 IDM re a 0.2 n) tp =10µs DS (o O is per lim ati ite on d in by th R is a 10 1 10 0 10 0 V(BR)DSS RDS(on) max. tp =1ms 10 1 ID(A) 10-2 Single pulse tp =10ms VDS (V) 10 2 10-3 -6 10 10-5 10-4 10-3 10-2 10-1 100 tp(s) Figure 4. Transfer characteristics Figure 3. Output characteristics GIPG161220141431ALS VGS = 6,7,8,9,10 V ID (A) GIPG161220141436ALS 25 25 VGS = 5 V 20 20 15 15 10 10 VGS = 4 V 5 0 0.05 0.02 0.01 tp =100µs TC = 25 °C TJ ≤ 150 °C VGS=10 V single pulse 10 -1 10 -1 0.1 10-1 8 4 0 12 16 5 GIPG161220141455ALS 12 VDS (V) 2 0 500 8 400 6 300 4 200 2 100 4 8 6 VGS(V) Figure 6. Static drain-source on-resistance RDS(on) (Ω) GADG160720200928RID 600 VDS = 520V ID = 12A 10 0 VDS(V) Figure 5. Gate charge vs gate-source voltage VGS (V) VDS = 16 v VGS = 10 A 0.300 0.290 0 0 DS10248 - Rev 4 4 8 12 16 20 0 Qg(nC) 0.280 0.270 0 2 4 6 8 ID (A) page 5/15 STL18N65M2 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) GIPG161220141520ALS GIPG161220141616ALS 6 1000 Ciss 5 4 100 3 Coss 2 10 1 1 0.1 1 10 Crss VDS(V) 100 Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm) GIPG161220141528ALS 600 VDS(V) RDS(on) (norm) GIPG161220141538ALS VGS = 10 V 1.0 0.8 0.6 0.7 -25 25 75 125 TJ(°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm) GIPG121620141601ALS 1.08 0.2 -75 TJ(°C) 125 Figure 12. Source-drain diode forward characteristics VSD (V) 1.00 0.6 0.96 0.4 0.92 0.2 25 75 GADG160720200940SDF Tj = -50 °C Tj = 25 °C 0.8 ID = 1 mA -25 25 -25 1.0 1.04 DS10248 - Rev 4 400 500 200 300 Figure 10. Normalized on-resistance vs temperature 1.4 0.9 0.88 -75 100 1.8 1.0 0.6 -75 0 2.2 ID = 250 µA 1.1 0 75 125 TJ(°C) 0.0 0 Tj = 150 °C 2 4 6 8 ISD (A) page 6/15 STL18N65M2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS10248 - Rev 4 page 7/15 STL18N65M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS10248 - Rev 4 page 8/15 STL18N65M2 PowerFLAT 5x6 HV package information 4.1 PowerFLAT 5x6 HV package information Figure 19. PowerFLAT 5x6 HV package outline 8368143_Rev_4 DS10248 - Rev 4 page 9/15 STL18N65M2 PowerFLAT 5x6 HV package information Table 7. PowerFLAT 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 20. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS10248 - Rev 4 page 10/15 STL18N65M2 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 21. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 22. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS10248 - Rev 4 page 11/15 STL18N65M2 PowerFLAT 5x6 packing information Figure 23. PowerFLAT 5x6 reel DS10248 - Rev 4 page 12/15 STL18N65M2 Revision history Table 8. Document revision history Date Revision 14-Mar-2014 1 Changes First release. Updated title and features on cover page. 25-Mar-2014 2 Updated Table 4: On /off states and Table 5: Dynamic Inserted PTOT value in Table 2: Absolute maximum ratings. Minor text changes. Updated values in Table 2: Absolute maximum ratings, Table 4: On/off states, Table 5: Dynamic, Table 6: Switching times and Table 7: Source drain diode. 02-Oct-2014 3 Updated title, features and description in cover page. Minor text changes. Modified Table 1. Absolute maximum ratings. 20-Jul-2020 4 Added Section 2.1 Electrical characteristics (curves). Minor text changes. DS10248 - Rev 4 page 13/15 STL18N65M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS10248 - Rev 4 page 14/15 STL18N65M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS10248 - Rev 4 page 15/15