STL18N65M5

STL18N65M5 Datasheet N-channel 650 V, 215 mΩ typ., 15 A MDmesh M5 Power MOSFET in a PowerFLAT 5x6 HV package Features 1 2 3 4 PowerFLAT 5x6 HV D(5, 6, 7, 8) Order code VDS RDS(on) max. ID STL18N65M5 650 V 240 mΩ 15 A • Extremely low RDS(on) • • • Low gate charge and input capacitance Excellent switching performance 100% avalanche tested Applications • G(4) Switching applications Description S(1, 2, 3) NG4D5678S123_v2 This device is an N-channel Power MOSFET based on the MDmesh M5 innovative vertical process technology combined with the well-known PowerMESH horizontal layout. The resulting product offers extremely low on-resistance, making it particularly suitable for applications requiring high power and superior efficiency. Product status link STL18N65M5 Product summary Order code STL18N65M5 Marking 18N65M5 Package PowerFLAT 5x6 HV Packing Tape and reel DS9244 - Rev 3 - March 2022 For further information contact your local STMicroelectronics sales office. www.st.com STL18N65M5 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Gate-source voltage ±25 V Drain current (continuous) at TC = 25 °C 15 Drain current (continuous) at TC = 100 °C 9.4 IDM(2) Drain current (pulsed) 60 A PTOT Total power dissipation at TC = 25 °C 57 W IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max.) 4 A EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 210 mJ Peak diode recovery voltage slope 15 V/ns VGS ID(1) dv/dt(3) Tstg TJ Parameter Storage temperature range Operating junction temperature range -55 to 150 A °C °C 1. ID is limited by package. 2. Pulse width is limited by safe operating area. 3. ISD ≤ 15 A, di/dt ≤ 400 A/μs, VDS (peak) < V(BR)DSS, VDD = 400 V. Table 2. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance, junction-to-case 2.2 °C/W RthJB(1) Thermal resistance, junction-to-board 59 °C/W 1. When mounted on an 1-inch² FR-4, 2oz Cu board. DS9244 - Rev 3 page 2/15 STL18N65M5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 3. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. 650 Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 7.5 A VGS = 0 V, VDS = 650 V, TC = 125 Unit V VGS = 0 V, VDS = 650 V IDSS Max. 1 °C(1) 100 µA ±100 nA 4 5 V 215 240 mΩ Min. Typ. Max. Unit - 1240 - pF - 32 - pF - 3 - pF - 99 - pF - 30 - pF 3 1. Specified by design, not tested in production. Table 4. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Equivalent capacitance time related Co(er)(2) Equivalent capacitance energy related Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V VDS = 0 to 520 V, VGS = 0 V RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 3 - Ω Qg Total gate charge VDD = 520 V, ID = 7.5 A - 31 - nC Qgs Gate-source charge VGS = 0 to 10 V - 8 - nC Gate-drain charge (see Figure 15. Test circuit for gate charge behavior) - 14 - nC Qgd 1. Co(tr) is an equivalent capacitance that provides the same charging time as Coss while VDS is rising from 0 V to the stated value. 2. Co(er) is an equivalent capacitance that provides the same stored energy as Coss while VDS is rising from 0 V to the stated value. Table 5. Switching times Symbol Test conditions Min. Typ. Max. Unit td(v) Voltage delay time VDD = 400 V, ID = 9.5 A, - 36 - ns tr(v) Voltage rise time RG = 4.7 Ω, VGS = 10 V - 7 - ns tf(i) Current fall time (see Figure 16. Test circuit for inductive load switching and diode recovery times and Figure 19. Switching time waveform) - 9 - ns - 11 - ns tc(off) DS9244 - Rev 3 Parameter Crossing time page 3/15 STL18N65M5 Electrical characteristics Table 6. Source-drain diode Symbol ISD(1) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 15 A ISDM(2) Source-drain current (pulsed) - 60 A VSD(3) Forward on voltage ISD = 15 A, VGS = 0 V - 1.5 V trr Reverse recovery time ISD = 15 A, di/dt = 100 A/µs, - 290 ns Qrr Reverse recovery charge VDD = 100 V - 3.4 µC IRRM Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 23.5 A trr Reverse recovery time ISD = 15 A, di/dt = 100 A/µs, - 352 ns Qrr Reverse recovery charge VDD = 100 V, TJ = 150 °C - 4 µC Reverse recovery current (see Figure 16. Test circuit for inductive load switching and diode recovery times) - 24 A IRRM 1. ISD is limited by package. 2. Pulse width is limited by safe operating area. 3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS9244 - Rev 3 page 4/15 STL18N65M5 Electrical characteristics curves 2.1 Electrical characteristics (curves) Figure 2. Normalized transient thermal impedance Figure 1. Safe operating area ID (A) 101 100 K AM15764v1 ea ar s (on) i th S in R D n y it o d b ra te pe i O s lim i ZthPowerFlat_5x6 δ =0.5 0.2 10µs 10-1 0.1 0.05 0.02 0.01 100µs 1ms 10ms 10-2 Zth = k * RthJC δ = tp / Ƭ Single pulse 10-1 TJ = 150 °C TC = 25 °C Single pulse 10-2 10-1 100 101 VDS (V) 102 Figure 3. Typical output characteristics ID (A) 10-3 -6 10 tp Ƭ 10-5 10-4 10-3 10-2 10-1 100 tp(s) Figure 4. Typical transfer characteristics AM15765v1 AM15766v1 ID (A) VGS = 9, 10 V VDS = 25 V VDS=25V VDS (V) Figure 5. Typical gate charge characteristics VGS (V) AM15767v1 VDS VDD = 520 V, ID = 7.5 A VDS (V) VGS (V) Figure 6. Typical drain-source on-resistance RDS(on) (mΩ) AM15768v1 VGS = 10 V 25 DS9244 - Rev 3 30 35 Qg (nC) ID (A) page 5/15 STL18N65M5 Electrical characteristics curves Figure 7. Typical capacitance characteristics C (pF) Figure 8. Typical output capacitance stored energy Eoss (µJ) AM15769v1 AM15770v1 6 104 5 Ciss 103 3 102 101 Coss f = 1 MHz Crss 100 10-1 4 100 101 102 VDS (V) Figure 9. Normalized gate threshold voltage vs temperature 2 1 0 0 200 400 600 Figure 10. Normalized on-resistance vs temperature RDS(on) (norm.) 2.1 VGS(th) (norm.) 1.1 VDS (V) AM05460v1 VGS = 10 V ID = 250 µA 1.0 1.7 1.3 0.9 0.9 0.8 0.7 -50 0 50 100 TJ (°C) Figure 11. Normalized breakdown voltage vs temperature V(BR)DSS (norm.) 1.08 AM10399v1 0.5 -50 0 50 100 TJ (°C) Figure 12. Typical reverse diode forward characteristics VSD (V) AM05461v1 TJ = -50 °C 1.2 ID = 1 mA 1.0 1.04 0.8 TJ = 25 °C 1.00 0.6 TJ = 150 °C 0.4 0.96 0.2 0.92 -50 DS9244 - Rev 3 0 50 100 TJ (°C) 0.0 0 10 20 30 40 50 ISD (A) page 6/15 STL18N65M5 Electrical characteristics curves Figure 13. Typical switching energy vs gate resistance E (µJ) AM15771v1 VDD = 400 V VGS = 10 V ID = 9.5 A 160 Eon 120 80 Eoff 40 0 DS9244 - Rev 3 0 10 20 30 40 RG (Ω) page 7/15 STL18N65M5 Test circuits 3 Test circuits Figure 15. Test circuit for gate charge behavior Figure 14. Test circuit for resistive load switching times VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 17. Unclamped inductive load test circuit Figure 16. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A A B B B L 100 µH fast diode 3.3 µF D G + RG VD 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S _ D.U.T. Vi pulse width AM01470v1 AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ID V(BR)DSS VDS 90%ID 90%VDS VD IDM VGS 90%VGS ID VDD VDD 10%VDS 10%ID tr VDS td(V) AM01472v1 DS9244 - Rev 3 tf ID tc(off) AM05540v2 page 8/15 STL18N65M5 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 HV package information Figure 20. PowerFLAT 5x6 HV package outline 8368143_Rev_4 DS9244 - Rev 3 page 9/15 STL18N65M5 PowerFLAT 5x6 HV package information Table 7. PowerFLAT 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 C 5.60 5.80 6.00 D 5.10 5.20 5.30 D2 4.30 4.40 4.50 D4 4.60 4.80 5.00 E 6.05 6.15 6.25 E1 3.50 3.60 3.70 E2 3.10 3.20 3.30 E4 0.40 0.50 0.60 E5 0.10 0.20 0.30 E7 0.40 0.50 0.60 e 0.50 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 21. PowerFLAT 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_4_footprint DS9244 - Rev 3 page 10/15 STL18N65M5 PowerFLAT 5x6 packing information 4.2 PowerFLAT 5x6 packing information Figure 22. PowerFLAT 5x6 tape (dimensions are in mm) (I) Measured from centreline of sprocket hole to centreline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ±0.20. Base and bulk quantity 3000 pcs All dimensions are in millimeters (III) Measured from centreline of sprocket hole to centreline of pocket 8234350_Tape_rev_C Figure 23. PowerFLAT 5x6 package orientation in carrier tape Pin 1 identification DS9244 - Rev 3 page 11/15 STL18N65M5 PowerFLAT 5x6 packing information Figure 24. PowerFLAT 5x6 reel DS9244 - Rev 3 page 12/15 STL18N65M5 Revision history Table 8. Document revision history Date Version 24-Apr-2013 1 26-Jun-2013 2 Changes First release. – Modified: Figure 6, 15, 16, 17, 18. – Minor text changes. Updated title, Features and Internal schematic on cover page. 08-Mar-2022 3 Updated Table 1. Absolute maximum ratings. Updated Section 4 Package information. Minor text changes. DS9244 - Rev 3 page 13/15 STL18N65M5 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.1 PowerFLAT 5x6 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS9244 - Rev 3 page 14/15 STL18N65M5 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS9244 - Rev 3 page 15/15