STL19N60DM2

STL19N60DM2 N-channel 600 V, 0.280 Ω typ., 11 A MDmesh™ DM2 with fast diode Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - preliminary data Features 6 6 6 %RWWRPYLHZ * Order code VDS @ TJmax RDS(on)max ID STL19N60DM2 650 V 0.320 ȍ 11 A ' • Fast-recovery body diode • Extremely low gate charge and input capacitance 3RZHU)/$7Œ[+9 • Low on-resistance RDS(on) • 100% avalanche tested • Extremely high dv/dt ruggedness Figure 1. Internal schematic diagram D(3) • Zener-protected Applications • Switching applications Description G(1) S(2) AM01476v6 This high voltage N-channel Power MOSFET is part of the MDmesh DM2 fast recovery diode series. It offers very low recovery charge and time (Qrr, trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1. Device summary Order code Marking Package Packaging STL19N60DM2 19N60DM2 PowerFLAT™ 8x8 HV Tape and reel August 2014 DocID026785 Rev 1 1/13 www.st.com Contents STL19N60DM2 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 6 DocID026785 Rev 1 STL19N60DM2 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Gate-source voltage VGS Value Unit ± 25 V ID (1) Drain current (continuous) at TC = 25 °C 11 A ID (1) Drain current (continuous) at TC = 100 °C 6.8 A Drain current (pulsed) 44 A Total dissipation at TC = 25 °C 90 W IDM (1),(2) PTOT(1) IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) TBD A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) TBD mJ Peak diode recovery voltage slope 40 V/ns MOSFET dv/dt ruggedness 50 V/ns - 55 to 150 °C 150 °C Value Unit 1.39 °C/W 45 °C/W dv/dt (3) dv/dt (4) Tstg Storage temperature Tj Max. operating junction temperature 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area. 3. ISD ≤ 11 A, di/dt ≤ 400 A/μs, VDS(peak) < V(BR)DSS, VDD= 400 V 4. VDS ≤ 480 V Table 3. Thermal data Symbol Rthj-case Rthj-amb (1) Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max 1. When mounted on FR-4 board of inch², 2oz Cu. DocID026785 Rev 1 3/13 13 Electrical characteristics 2 STL19N60DM2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. On /off states Symbol V(BR)DSS Parameter Drain-source breakdown voltage IDSS Zero gate voltage drain current IGSS Gate-body leakage current Test conditions VGS = 0, ID = 1 mA Min. Typ. Max. Unit 600 V VGS = 0, VDS = 600V 1 μA VGS = 0, VDS = 600 V, TC=125 °C 100 μA VDS = 0, VGS = ± 25 V ±10 μA 4 5 V 0.280 0.320 ȍ Min. Typ. Max. Unit - TBD - pF VDS = 100 V, f = 1 MHz, VGS = 0 - TBD - pF - TBD - pF - TBD - pF 5.5 - ȍ - 21 - nC - TBD - nC - TBD - nC VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA RDS(on) Static drain-source onVGS = 10 V, ID = 5.5 A resistance 3 Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 RG Intrinsic gate resistance f = 1 MHz open drain Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 480 V, ID = 11 A, VGS = 10 V (see Figure 3) 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 4/13 DocID026785 Rev 1 STL19N60DM2 Electrical characteristics Table 6. Switching times Symbol td(on) tr Parameter Test conditions Turn-on delay time VDD = 300 V, ID = 5.5 A, RG = 4.7 ȍ, VGS = 10 V (see Figure 2 and 7) Voltage rise time td(off) Turn-off delay time Current fall time tf Min. Typ. Max. Unit - TBD - ns - TBD - ns - TBD - ns - TBD - ns Min. Typ. Table 7. Source drain diode Symbol ISD(1) ISDM (1),(2) VSD trr (3) (4) Qrr (4) IRRM trr (4) (4) Qrr (4) IRRM (4) Parameter Test conditions Max. Unit Source-drain current - 11 A Source-drain current (pulsed) - 44 A - 1.5 V Forward on voltage ISD = 11A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 11A, di/dt = 100A/μs VDD = 100 V (see Figure 4) ISD = 11 A, di/dt = 100A/μs VDD = 100 V, Tj = 150 °C (see Figure 4) - 120 ns - TBD μC - TBD A - TBD ns - TBD μC - TBD A 1. The value is rated according to Rthj-case and limited by package. 2. Pulse width limited by safe operating area 3. Pulsed: pulse duration = 300 μs, duty cycle 1.5% 4. Typical values are referring to the test conditions of the same die housed in through hole package. The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD capability of the device. The Zener voltage is appropriate for efficient and costeffective intervention to protect the device integrity. These integrated Zener diodes thus eliminate the need for external components. DocID026785 Rev 1 5/13 13 Test circuits 3 STL19N60DM2 Test circuits Figure 2. Switching times test circuit for resistive load Figure 3. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF IG=CONST VDD VGS 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 Figure 4. Test circuit for inductive load switching and diode recovery times A A AM01469v1 Figure 5. Unclamped inductive load test circuit L A D G FAST DIODE D.U.T. S 3.3 μF B B B VD L=100μH 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 6/13 0 DocID026785 Rev 1 10% AM01473v1 STL19N60DM2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026785 Rev 1 7/13 13 Package mechanical data STL19N60DM2 Figure 8. PowerFLAT™ 8x8 HV drawing mechanical data 8222871_REV_C 8/13 DocID026785 Rev 1 STL19N60DM2 Package mechanical data Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.95 1.00 1.05 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e L 2.00 0.40 0.50 0.60 Figure 9. PowerFLAT™ 8x8 HV recommended footprint (dimensions in mm.) 8222871_REV_C_footprint DocID026785 Rev 1 9/13 13 Packaging mechanical data 5 STL19N60DM2 Packaging mechanical data Figure 10. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) B0 (8.30±0.1) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk quantity 3000 pcs 8229819_Tape_revA Figure 11. PowerFLAT™ 8x8 HV package orientation in carrier tape 10/13 DocID026785 Rev 1 STL19N60DM2 Packaging mechanical data Figure 12. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA DocID026785 Rev 1 11/13 13 Revision history 6 STL19N60DM2 Revision history Table 9. Document revision history 12/13 Date Revision 08-Aug-2014 1 Changes First release. DocID026785 Rev 1 STL19N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID026785 Rev 1 13/13 13