STL19N60M2

STL19N60M2 Datasheet N-channel 600 V, 0.278 Ω typ., 11 A MDmesh M2 Power MOSFET in a PowerFLAT 8x8 HV package Features 5 4 3 2 1 PowerFLAT 8x8 HV Order code VDS RDS(on) max. ID STL19N60M2 600 V 0.308 Ω 11 A • • Extremely low gate charge Excellent output capacitance (COSS) profile • • 100% avalanche tested Zener-protected Drain(5) Applications • Switching applications Gate(1) Description Driver source (2) Power source (3, 4) NG1DS2PS34D5Z This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Product status link STL19N60M2 Product summary Order code STL19N60M2 Marking 19N60M2 Package PowerFLAT 8x8 HV Packing Tape and reel DS11488 - Rev 3 - June 2019 For further information contact your local STMicroelectronics sales office. www.st.com STL19N60M2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V ID Drain current (continuous) at TC = 25 °C 11 A ID Drain current (continuous) at TC = 100 °C 6.9 A Drain current (pulsed) 44 A Total power dissipation at TC = 25 °C 90 W Peak diode recovery voltage slope 15 V/ns MOSFET dv/dt ruggedness 50 V/ns -55 to 150 °C Value Unit IDM (1) PTOT dv/dt (2) dv/dt (3) Tstg TJ Storage temperature range Operating junction temperature range 1. Pulse width limited by safe operating area. 2. ISD ≤ 11 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. 3. VDS ≤ 480 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 1.39 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 45 °C/W Value Unit 3 A 135 mJ 1. When mounted on FR-4 board of inch², 2oz Cu. Table 3. Avalanche characteristics Symbol DS11488 - Rev 3 Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by TJ max) EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR; VDD = 50 V) page 2/14 STL19N60M2 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 600 V, TC = 125 °C (1) 100 µA IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V 0.278 0.308 Ω Min. Typ. Max. Unit - 791 - pF - 40 - pF - 1.3 - pF VGS(th) RDS(on) Static drain-source 2 VGS = 10 V, ID = 5.5 A on-resistance 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Test conditions VDS= 100 V, f = 1 MHz, VGS = 0 V Reverse transfer capacitance (1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 164.5 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.6 - Ω Qg Total gate charge VDD = 480 V, ID = 13 A, - 21.5 - nC Qgs Gate-source charge - 3.2 - nC Qgd Gate-drain charge VGS = 0 to 10 V (see Figure 14. Test circuit for gate charge behavior) - 11.3 - nC Coss eq. 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11488 - Rev 3 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 6.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) Min. Typ. Max. Unit - 12 - ns - 9 - ns - 47 - ns - 10.6 - ns page 3/14 STL19N60M2 Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 11 A ISDM (1) Source-drain current (pulsed) - 44 A VSD (2) Forward on voltage VGS = 0 V, ISD = 11 A - 1.6 V trr Reverse recovery time - 305 ns Qrr Reverse recovery charge - 3.3 µC IRRM Reverse recovery current ISD = 13 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 15. Test circuit for inductive load switching and diode recovery times ) - 22 A Reverse recovery time ISD = 13 A, di/dt = 100 A/µs, - 417 ns Qrr Reverse recovery charge - 4.6 µC IRRM Reverse recovery current VDD = 60 V, TJ = 150 °C (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 22 A trr 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DS11488 - Rev 3 page 4/14 STL19N60M2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GIPD250120161513SOA Zth PowerFLAT 8x8 HV K δ=0.5 0.2 Operation in this area is limited by RDS(on) 10 tp = 10 µs tp = 100 µs 1 0.1 -1 10 0.02 tp = 1ms single pulse, TC = 25°C, TJ ≤ 150°C, VGS = 10 V Zth= K*R thJ-c δ= t p/Ƭ 0.01 tp = 10 ms Single pulse tp 0.1 -2 1 0.1 10 100 10 -5 10 VDS (V) Figure 3. Output characteristics AM15838v1 VDS = 18V 25 6V 20 20 15 15 10 10 5V 5 5 4V 0 0 5 15 10 20 AM15839v1 VDS VDD = 480 V ID = 13 A 10 0 0 VDS(V) Figure 5. Gate charge vs gate-source voltage RDS(on) (Ω) 500 0.295 400 300 6 2 4 10 8 6 VGS(V) Figure 6. Static drain-source on-resistance VDS (V) 8 GIPG260120161632RID VGS =10 V 0.290 0.285 0.280 200 4 0.275 100 2 0 0 tp (s) 10 10 30 25 12 Ƭ -2 -3 10 ID (A) VGS=7, 8, 9, 10V 30 VGS (V) -4 Figure 4. Transfer characteristics AM15837v1 ID (A) DS11488 - Rev 3 0.05 5 10 15 20 25 0 Qg (nC) 0.270 0.265 0 2 4 6 8 10 ID (A) page 5/14 STL19N60M2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations AM15841v1 C (pF) VGS(th) (norm.) GIPG070815BQ6KLVTH ID = 250 µA 1.1 1000 Ciss 1.0 100 0.9 Coss 0.8 10 0.7 1 0.1 1 100 10 Crss VDS (V) Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GIPG070815BQ6KLRON VGS = 10 V 2.4 0.6 -75 1.04 1.2 1.00 0.8 0.96 0.4 0.92 75 125 TJ (°C) Figure 11. Output capacitance stored energy AM15843v1 Eoss (µJ) DS11488 - Rev 3 0.88 -75 5 1.0 4 0.9 3 0.8 2 0.7 1 0.6 300 400 ID = 1 mA 500 600 VDS (V) -25 25 75 VSD (V) 1.1 100 200 TJ (°C) 125 TJ (°C) Figure 12. Source-drain diode forward characteristics 6 0 0 125 GIPG070815BQ6KLBDV 1.12 1.6 25 75 V(BR)DSS (norm.) 1.08 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 2.0 0.0 -75 -25 0.5 0 GIPG260120161706SDF 2 4 6 8 10 ISD (A) page 6/14 STL19N60M2 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD 12V 47kΩ 1kΩ 100nF + VD VGS 3.3 µF 2200 RL µF IG=CONST VDD 2200 µF + RG 100Ω Vi ≤ VGS D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ GND1 (driver signal) GND2 (power) 1kΩ PW GND1 AM15855v1 Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE S A L L=100µH D 25Ω VD 3.3 µF B B B AM15856v1 Figure 16. Unclamped inductive load test circuit D G GND2 + 1000 µF 2200 µF + VDD 3.3 µF VDD ID G S RG D.U.T. Vi Pw GND2 GND1 D.U.T. GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform ton Figure 17. Unclamped inductive waveform td(on) toff td(off) tr tf V(BR)DSS VD 90% 90% IDM ID VDD 10% 0 VDS 10% VDD VGS 90% AM01472v1 0 10% AM01473v1 DS11488 - Rev 3 page 7/14 STL19N60M2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 PowerFLAT 8x8 HV package information Figure 19. PowerFLAT 8x8 HV package outline 8222871_Rev_4 DS11488 - Rev 3 page 8/14 STL19N60M2 PowerFLAT 8x8 HV package information Table 8. PowerFLAT 8x8 HV mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 20. PowerFLAT 8x8 HV footprint 8222871_REV_4_footprint Note: DS11488 - Rev 3 All dimensions are in millimeters. page 9/14 STL19N60M2 PowerFLAT 8x8 HV packing information 4.2 PowerFLAT 8x8 HV packing information Figure 21. PowerFLAT 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 22. PowerFLAT 8x8 HV package orientation in carrier tape DS11488 - Rev 3 page 10/14 STL19N60M2 PowerFLAT 8x8 HV packing information Figure 23. PowerFLAT 8x8 HV reel 8229819_Reel_revA Note: DS11488 - Rev 3 All dimensions are in millimeters. page 11/14 STL19N60M2 Revision history Table 9. Document revision history Date Revision Changes 27-Jan-2016 1 First release. 15-Nov-2018 2 Updated Table 1. Absolute maximum ratings, Table 2. Thermal data, Table 4. On/off states, Table 5. Dynamic, Table 6. Switching times, Table 7. Source drain diode and Figure 7. Capacitance variations. Updated description in cover page. 11-Jun-2019 3 Updated Table 5. Dynamic and Table 6. Switching times. Minor text changes. DS11488 - Rev 3 page 12/14 STL19N60M2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT 8x8 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS11488 - Rev 3 page 13/14 STL19N60M2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS11488 - Rev 3 page 14/14