STL20DNF06LAG

STL20DNF06LAG Automotive-grade dual N-channel 60 V, 27 mΩ typ., 20 A STripFET™ II Power MOSFET in a PowerFLAT™ 5x6 double island package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STL20DNF06LAG 60 V 40 mΩ 20 A 75 W     Designed for Automotive applications and AEC-Q101 qualified PowerFLAT™ 5x6 double island with wettable flanks Logic level VGS(th) Maximum junction temperature: TJ = 175 °C Applications Figure 1: Internal schematic diagram  Switching applications Description This Power MOSFET series realized with STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer applications. It is also suitable for any application with low gate charge drive requirements. Table 1: Device summary Order code Marking Package Packing STL20DNF06LAG 20DNF06L PowerFLAT™ 5x6 double island Tape and reel September 2015 DocID028242 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STL20DNF06LAG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT™ 5x6 double island WF type R package information .... 9 4.2 PowerFLAT™ 5x6 WF packing information .................................... 12 Revision history ............................................................................ 14 DocID028242 Rev 1 STL20DNF06LAG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V Drain current (continuous) at Tcase = 25 °C 20 Drain current (continuous) at Tcase = 100 °C 20 Drain current (pulsed) 80 Drain current (continuous) at Tpcb = 25 °C 7.4 Drain current (continuous) at Tpcb = 100 °C 5.2 Drain current (pulsed) 29.6 ID(1)(2) IDM(1)(3) ID(4) IDM PTOT Total dissipation at Tcase = 25 °C 75 PTOT Total dissipation at Tpcb = 25 °C 4.8 Tstg Storage temperature Tj Operating junction temperature A A A A W -55 to 175 °C Value Unit Notes: (1)This value is rated according to Rthj-c. (2)Current limited by package. (3) Pulse width is limited by safe operating area. (4) This value is rated according to Rthj-pcb. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.0 Thermal resistance junction-pcb 31.3 Rthj-pcb (1) °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. Table 4: Avalanche characteristics Symbol IAV EAS(1) Parameter Value Unit Avalanche current, not repetitive 7.4 A Single pulse avalanche energy 210 mJ Notes: (1) starting Tj = 25 °C, ID = IAV, per channel. DocID028242 Rev 1 3/15 Electrical characteristics 2 STL20DNF06LAG Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 µA Min. Typ. Max. 60 Unit V VGS = 0 V, VDS = 60 V 1 µA VGS = 0 V, VDS = 60 V, TC = 125 °C 100 µA Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 4 A 27 40 VGS = 5 V, ID = 4 A 32 50 Min. Typ. Max. - 670 - - 170 - - 56 - - 22.5 - - 2.5 - - 7 - Min. Typ. Max. - 7 - - 15.4 - - 36.8 - - 7.7 - IDSS Zero gate voltage drain current IGSS 1 mΩ Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDD = 25 V, ID = 7.4 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") Unit pF nC Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 30 V, ID = 3.7 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") DocID028242 Rev 1 Unit ns STL20DNF06LAG Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 7.4 A ISDM(1) Source-drain current (pulsed) - 29.6 A VSD(2) Forward on voltage VGS = 0 V, ISD = 7.4 A - 1.5 V trr Reverse recovery time - 28 ns Qrr Reverse recovery charge - 31.6 nC IRRM Reverse recovery current ISD = 7.4 A, di/dt = 100 A/µs, VDD = 48 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 2.26 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID028242 Rev 1 5/15 Electrical characteristics 2.1 6/15 STL20DNF06LAG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028242 Rev 1 STL20DNF06LAG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature (VGS = 5 V) Figure 11: Normalized on-resistance vs temperature (VGS = 10 V) Figure 12: Normalized V(BR)DSS vs temperature Figure 13: Source-drain diode forward characteristics DocID028242 Rev 1 7/15 Test circuits 3 STL20DNF06LAG Test circuits Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform 8/15 DocID028242 Rev 1 Figure 19: Switching time waveform STL20DNF06LAG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 PowerFLAT™ 5x6 double island WF type R package information Figure 20: PowerFLAT™ 5x6 double island WF type R package outline DocID028242 Rev 1 9/15 Package information STL20DNF06LAG Table 9: PowerFLAT™ 5x6 double island WF type R mechanical data mm Dim. Min. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 D 5.00 D2 1.68 E 6.20 E2 3.50 E4 0.55 0.75 E5 0.08 0.28 E6 2.35 2.55 E7 0.40 0.60 e L K 0.50 5.20 5.40 1.88 6.40 6.60 3.70 1.27 0.70 L1 10/15 Typ. 0.90 0.275 1.275 DocID028242 Rev 1 1.575 STL20DNF06LAG Package information Figure 21: PowerFLAT™ 5x6 double island recommended footprint (dimensions are in mm) DocID028242 Rev 1 11/15 Package information 4.2 STL20DNF06LAG PowerFLAT™ 5x6 WF packing information Figure 22: PowerFLAT™ 5x6 WF tape Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape 12/15 DocID028242 Rev 1 STL20DNF06LAG Package information Figure 24: PowerFLAT™ 5x6 reel DocID028242 Rev 1 13/15 Revision history 5 STL20DNF06LAG Revision history Table 10: Document revision history 14/15 Date Revision 29-Sep-2015 1 DocID028242 Rev 1 Changes First release. STL20DNF06LAG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028242 Rev 1 15/15