STL23NS3LLH7

STL23NS3LLH7 N-channel 30 V, 0.0027 Ω typ., 23 A STripFET™ H7 Power MOSFET plus monolithic Schottky in a PowerFLAT™ 3.3 x 3.3 Datasheet - production data Features     Order code VDS RDS(on) max ID STL23NS3LLH7 30 V 0.0037 Ω 23 A Very low on-resistance Very low Qg High avalanche ruggedness Embedded Schottky diode Applications  Figure 1: Internal schematic diagram Switching applications Description This N-channel Power MOSFET utilizes the STripFET H7 technology with a trench gate structure combined with extremely low onresistance. The device also offers ultra-low capacitances for higher switching frequency operations. D(5, 6, 7, 8) G(4) S(1, 2, 3) Table 1: Device summary Order code STL23NS3LLH7 May 2015 Marking 23NS3 Package PowerFLAT DocID025074 Rev 3 This is information on a product in full production. TM 3.3 x 3.3 Packing Tape and reel 1/14 www.st.com Contents STL23NS3LLH7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/14 PowerFlat 3.3 x 3.3 package information ........................................ 10 Revision history ............................................................................ 13 DocID025074 Rev 3 STL23NS3LLH7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 30 V VGS Gate-source voltage ± 20 V (1) ID Drain current (continuous) at Tpcb = 25 °C 23 A (1) ID Drain current (continuous) at Tpcb = 100 °C 14.3 A (1)(2) IDM Drain current (pulsed) 92 A (3) ID Drain current (continuous) at Tc = 25 °C 92 A (3) ID Drain current (continuous) at Tc = 100 °C 57.5 A Drain current (pulsed) 368 A (2)(3) IDM PTOT (1) Total dissipation at TC = 25 °C 50 W PTOT (3) Total dissipation at Tpcb = 25 °C 2.9 W -55 to 150 °C Tstg Storage temperature Tj Operating junction temperature Notes: (1) (2) (3) This value is rated according to Rthj-c. Pulse width limited by safe operating area. This value is rated according to Rthj-pcb. Table 3: Thermal data Symbol Rthj-pcb (1) Rthj-case Parameter Value Unit Thermal resistance junction-pcb max 42.8 °C/W Thermal resistance junction-case max 2.5 °C/W Notes: (1) When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec. DocID025074 Rev 3 3/14 Electrical characteristics 2 STL23NS3LLH7 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage ID = 1 mA, VGS = 0 V IDSS Zero gate voltage drain current VGS = 0 V VDS = 24 V 500 µA IGSS Gate-body leakage current VGS = ± 20 V, VDS = 0 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 1 mA 2.3 V RDS(on) Static drain-source on-resistance V(BR)DSS 30 V 1.2 VGS = 10 V, ID = 11.5 A 0.0027 0.0037 Ω VGS = 4.5 V, ID = 11.5 A 0.004 0.005 Ω Table 5: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 15 V, f = 1 MHz, VGS = 0 V VDD = 10 V, ID = 23 A, VGS = 4.5 V (see Figure 13: "Gate charge test circuit") Min. Typ. Max. Unit - 2100 - pF - 850 - pF - 60 - pF - 13.7 - nC - 7.5 - nC - 3.3 - nC Table 6: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 15 V, ID = 11.5 A, RG = 3 Ω, VGS = 4.5 V Fall time DocID025074 Rev 3 Min. Typ. Max. Unit - 10 - ns - 33 - ns - 22 - ns - 7.5 - ns STL23NS3LLH7 Electrical characteristics Table 7: Source drain diode Symbol (1) VSD Parameter Test conditions Min. Typ. Max. Unit 0.7 V Forward on voltage ISD = 2 A, VGS = 0 - 0.4 trr Reverse recovery time - 31.2 ns Qrr Reverse recovery charge - 18.7 nC IRRM Reverse recovery current ISD = 2 A, di/dt = 100 A/µs VGS = 0 V - 1.2 A Notes: (1) Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID025074 Rev 3 5/14 Electrical characteristics 2.1 STL23NS3LLH7 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance GIPG200220151051MT GIPG200220151026MT ID (A) δ ) S( on D O pe m rati ite on d by i n t m hi s ax a R rea is 0.2 0.1 0.05 Li 100 0.02 100µs 10 0.01 1ms Tj=150°C Tc=25°C Single pulse 1 0.1 1 10ms V DS(V) 10 Figure 4: Output characteristics Figure 5: Transfer characteristics GIPG200220151112MT ID(A) V GS=5, 6, 7V GIPG200220151115MT ID (A) 100 40 4V 30 20 50 3V VDS = 2 V 10 0 0 0.8 0.4 0 1.2 1.6 V DS(V) Figure 6: Gate charge vs gate-source voltage GIPG200220151123MT V GS (V) 0 V GS(V) 2 Figure 7: Static drain-source on-resistance GIPG200220151129MT R DS(on) (mOhm) 3.00 5 V GS=10V 2.90 V DD=15V ID=23 A 4 2.80 2.70 3 2.60 2 2.50 1 0 0 6/14 2.40 2.30 2 4 6 8 10 12 14 Q g(nC) DocID025074 Rev 3 0 5 10 15 20 25 ID(A) STL23NS3LLH7 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized on-resistance vs temperature GIPG200220151138MT C (pF) Ciss 1000 Coss GIPG200220151338MT R DS(on) (norm) 1.90 1.70 1.50 V GS=10V Id=11.5A 1.30 1.10 100 0.90 Crss 0.70 10 0.1 1 10 V DS(V) Figure 10: Normalized V(BR)DSS vs temperature GIPG200220151327MT V (BR)DSS (norm) 0.50 -75 25 -25 75 125 T J(°C) Figure 11: Source-drain diode forward characteristics GIPG200220151216MT V SD(V) 1.06 T J=-50°C 0.85 1.04 ID=1m A 0.75 T J=25°C 1.02 0.65 1.00 0.98 0.55 0.96 0.45 0.94 -75 -25 25 75 125 T J(°C) 0.35 DocID025074 Rev 3 T J=150°C 0 10 20 ISD(A) 7/14 Test circuits 3 STL23NS3LLH7 Test circuits Figure 12: Switching times test circuit for resistive load Figure 13: Gate charge test circuit Figure 14: Test circuit for inductive load switching and diode recovery times Figure 15: Unclamped inductive load test circuit Figure 16: Unclamped inductive waveform Figure 17: Switching time waveform 8/14 DocID025074 Rev 3 STL23NS3LLH7 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025074 Rev 3 9/14 Package information 4.1 STL23NS3LLH7 PowerFlat 3.3 x 3.3 package information Figure 18: PowerFLAT™ 3.3 x 3.3 package outline 10/14 DocID025074 Rev 3 STL23NS3LLH7 Package information Table 8: PowerFLAT™ 3.3 x 3.3 mechanical data mm Dim. Min. Typ. Max. A 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 D 3.10 3.30 3.50 D1 3.05 3.15 3.25 D2 2.15 2.25 2.35 e 0.55 0.65 0.75 E 3.10 3.30 3.50 E1 2.90 3.00 3.10 E2 1.60 1.70 1.80 H 0.25 0.40 0.55 K 0.65 0.75 0.85 L 0.30 0.45 0.60 L1 0.05 0.15 0.25 L2 θ 0.15 8° DocID025074 Rev 3 10° 12° 11/14 Package information STL23NS3LLH7 Figure 19: PowerFLAT™ 3.3 x 3.3 recommended footprint (dimension in millimeters) 12/14 DocID025074 Rev 3 STL23NS3LLH7 5 Revision history Revision history Table 9: Document revision history Date Revision Changes 31-Jul-2013 1 First release. 27-Mar-2015 2 Updated title and features in cover page. Updated Table 2: "Absolute maximum ratings", Table 4: "On /off states" and Table 7: "Source drain diode". Added Section 2.1: "Electrical characteristics (curves)". Minor text changes. 07-May-2015 3 Document status promoted from preliminary data to production data. Minor text changes. DocID025074 Rev 3 13/14 STL23NS3LLH7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 14/14 DocID025074 Rev 3