STL24N60DM2

STL24N60DM2 N-channel 600 V, 0.195 Ω typ., 15 A MDmesh™ DM2 Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet - production data Features 5 4 3 2 Order code VDS @ TJmax RDS(on) max. ID STL24N60DM2 650 V 0.220 Ω 15 A   1     PowerFLAT™ 8x8 HV Figure 1: Internal schematic diagram Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STL24N60DM2 24N60DM2 PowerFLAT™ 8x8 HV Tape and reel July 2016 DocID026017 Rev 3 This is information on a product in full production. 1/15 www.st.com Contents STL24N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 PowerFLAT8x8 HV package information ........................................ 10 4.2 PowerFLAT8x8 HV packaging information ..................................... 12 Revision history ............................................................................ 14 DocID026017 Rev 3 STL24N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS ID(1) IDM(1)(2) PTOT (1) Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 15 Drain current (continuous) at Tcase = 100 °C 9.5 Drain current (pulsed) 60 A W Total dissipation at Tcase = 25 °C 125 dv/dt(3) Peak diode recovery voltage slope 40 dv/dt(4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range A V/ns -55 to 150 °C Notes: (1)The value is limited by package (2)Pulse (3)I (4) SD width limited by safe operating area. ≤ 15 A, di/dt ≤ 400 A/μs, VDS(peak) < V(BR)DSS, VDD=400 V VDS ≤ 480 V. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 1 Thermal resistance junction-pcb 45 Rthj-pcb (1) Value Unit °C/W Notes: (1)When mounted on FR-4 board of inch², 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 3 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 160 mJ DocID026017 Rev 3 3/15 Electrical characteristics 2 STL24N60DM2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: On/off-state Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 V VGS = 0 V, VDS = 600 V 1.5 VGS = 0 V, VDS = 600 V, Tcase = 125 °C 100 IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 9 A Unit µA ±10 µA 4 5 V 0.195 0.220 Ω Min. Typ. Max. Unit - 1055 - - 56 - - 2.4 - 3 Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 259 - pF RG Intrinsic gate resistance f = 1 MHz, ID= 0 A - 7 - Ω Qg Total gate charge - 29 - Qgs Gate-source charge - 6 - Qgd Gate-drain charge VDD = 480 V, ID = 18 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") - 12 - VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 300 V, ID = 9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 15 - - 8.7 - - 60 - - 15 - DocID026017 Rev 3 Unit ns STL24N60DM2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter ISD(1) Source-drain current ISDM(2) Source-drain current (pulsed) VSD(3) Forward on voltage trr Test conditions VGS = 0 V, ISD = 18 A Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: " Test circuit for inductive load switching and diode recovery times") trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 18 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: " Test circuit for inductive load switching and diode recovery times") Min. Typ. Max. Unit - 15 A - 60 A - 1.6 V - 155 ns - 956 nC - 12.5 A - 200 ns - 1450 nC - 13 A Notes: (1)The value is limited by package. (2)Pulse (3) width limited by safe operating area Pulsed: pulse duration = 300 μs, duty cycle 1.5% DocID026017 Rev 3 5/15 Electrical characteristics 2.1 STL24N60DM2 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area K δ=0.5 0.2 0.1 10 -1 0.05 0.02 Zth= K*RthJ-c δ= tp/Ƭ 0.01 Single pulse tp -2 10 -5 10 10 -4 10 -3 10 Ƭ -2 tp (s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance R Ω VGS=10 V 0.204 0.200 0.196 0.192 0.188 0.184 0 6/15 DocID026017 Rev 3 2 4 6 8 10 12 14 ID(A) STL24N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature RDS(on) (norm) 2.5 ID=9 A VGS=10 V 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -50 -25 0 25 50 75 100 125 TJ(°C) Figure 12: Output capacitance stored energy AM15669v1 Eoss(µJ) Figure 13: Source- drain diode forward characteristics 8 7 6 5 4 3 2 1 0 0 100 200 300 400 500 600 VDS(V) DocID026017 Rev 3 7/15 Test circuits 3 STL24N60DM2 Test circuits Figure 15: Gate charge test circuit Figure 14: Switching times test circuit for resistive load 3.3 µF 2200 RL + µF VDD VD VGS RG D.U.T. PW GND1 (driver signal) GND2 (power) Figure 16: Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE B B Figure 17: Unclamped inductive load test circuit A D G S L=100µH 3.3 µF B 25Ω L D + 1000 µF VD 2200 µF VDD VDD + G RG 3.3 µF ID S D.U.T. Vi GND1 D.U.T. GND2 Pw GND1 Figure 18: Unclamped inductive waveform 8/15 DocID026017 Rev 3 GND2 AM15858v1 Figure 19: Switching time waveform STL24N60DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID026017 Rev 3 9/15 Package information 4.1 STL24N60DM2 PowerFLAT8x8 HV package information Figure 20: PowerFLAT™ 8x8 HV package outline 8222871_Rev_3_ A 10/15 DocID026017 Rev 3 STL24N60DM2 Package information Table 9: PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 0.05 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 2.00 0.40 0.50 0.60 Figure 21: PowerFLAT™ 8x8 HV footprint All dimensions are in millimeters. DocID026017 Rev 3 11/15 Package information 4.2 STL24N60DM2 PowerFLAT8x8 HV packaging information Figure 22: PowerFLAT™ 8x8 HV tape All dimensions are in millimeters. Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape 12/15 DocID026017 Rev 3 STL24N60DM2 Package information Figure 24: PowerFLAT™ 8x8 HV reel All dimensions are in millimeters. DocID026017 Rev 3 13/15 Revision history 5 STL24N60DM2 Revision history Table 10: Document revision history 14/15 Date Revision Changes 03-Mar-2014 1 First release. 21-Jan-2016 2 Modified: title, features, description and internal schematic in cover page Modified: Section 3: "Test circuits" Updated: Section 4: "Package information" Minor text changes 25-Jul-2016 3 Document status promoted from preliminary to production data. DocID026017 Rev 3 STL24N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID026017 Rev 3 15/15