STL24N60M6

STL24N60M6 Datasheet N-channel 600 V, 0.175 Ω typ., 15 A, MDmesh™ M6 Power MOSFET in a PowerFLAT™ 8x8 HV package Features 5 4 3 2 1 PowerFLAT™ 8x8 HV Drain(5) Order code VDS RDS(on) max. ID STL24N60M6 600 V 209 mΩ 15 A • • Reduced switching losses Lower RDS(on) per area vs previous generation • • • Low gate input resistance 100% avalanche tested Zener-protected Applications • • • Gate(1) Driver source (2) Power source (3, 4) NG1DS2PS34D5Z Product status link Switching applications LLC converters Boost PFC converters Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent RDS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. STL24N60M6 Product summary Order code STL24N60M6 Marking 24N60M6 Package PowerFLAT™ 8x8 HV Packing Tape and reel DS12706 - Rev 1 - August 2018 For further information contact your local STMicroelectronics sales office. www.st.com STL24N60M6 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS ID Parameter Value Unit Gate-source voltage ±25 V Drain current (continuous) at Tcase = 25 °C 15 Drain current (continuous) at Tcase = 100 °C 9 A IDM(1) Drain current (pulsed) 52.5 A PTOT Total dissipation at Tcase = 25 °C 109 W dv/dt(2) Peak diode recovery voltage slope 15 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj V/ns -55 to 150 °C Value Unit Thermal resistance junction-case 1.15 °C/W Thermal resistance junction-pcb 50 °C/W Value Unit 3.2 A 250 mJ Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 15 A, di/dt = 400 A/μs, VDS < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on FR-4 board of inch², 2oz Cu. Table 3. Avalanche characteristics Symbol IAR EAS DS12706 - Rev 1 Parameter Avalanche current, repetitive or non-repetitive (pulse width limited by TJmax) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) page 2/15 STL24N60M6 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified). Table 4. On/off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current IGSS 1 VGS = 0 V, VDS = 600 V, Tcase = 125 100 °C(1) Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance ID = 8.5 A, VGS = 10 V Unit V VGS = 0 V, VDS = 600 V IDSS Max. µA ±5 µA 4 4.75 V 0.175 0.209 Ω Min. Typ. Max. Unit - 960 - - 76 - - 4.5 - 3.25 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 181 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5 - Ω Qg Total gate charge VDD = 480 V, ID = 17 A, - 23 - Qgs Gate-source charge VGS = 0 to 10 V - 4.8 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 12.8 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12706 - Rev 1 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 8.5 A, - 17.7 - Rise time RG = 4.7 Ω, VGS = 10 V - 32 - Turn-off delay time (see Figure 13. Switching times test circuit for resistive load and Figure 18. Switching time waveform) - 38.3 - - 9 - Fall time Unit ns page 3/15 STL24N60M6 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM(1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 15 A Source-drain current (pulsed) - 52.5 A 1.6 V Forward on voltage ISD = 15 A, VGS = 0 V - trr Reverse recovery time ISD = 17 A, di/dt = 100 A/µs, - 225 ns Qrr Reverse recovery charge VDD = 60 V - 2.3 µC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 20.4 A trr Reverse recovery time ISD = 17 A, di/dt = 100 A/µs, - 307 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 3.85 µC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 25.1 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS12706 - Rev 1 page 4/15 STL24N60M6 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area ID (A) Figure 2. Thermal impedance GADG200720180951SOA K PowerFLAT8x8HVzth δ =0.5 10 1 Operation in this area is limited by RDS(on) δ =0.2 tp =10 µs δ =0.1 tp =100 µs 10 0 tp =1 ms δ =0.05 Z th =K*R thj-c δ=t p / Ƭ δ =0.02 tp =10 ms Single pulse, TC = 25 °C, TJ ≤ 150 °C, VGS = 10 V 10 -1 10 -1 δ =0.01 tp Single pulse 10 -2 10 -1 10 0 10 1 VDS (V) 10 2 10 -2 10 -5 Figure 3. Output characteristics ID (A) ID (A) VGS = 9, 10 V t p (s) 10 -2 GADG200720180952TCH 50 VGS = 8 V 40 10 -3 Figure 4. Transfer characteristics GADG200720180952OCH 50 10 -4 Ƭ VDS = 16 V 40 30 30 VGS = 7 V 20 20 10 0 0 10 VGS = 6 V 2 4 6 8 10 12 14 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GADG200720180952QVG VDS (V) 12 10 600 VDS 500 VDD = 480 V ID = 17 A 8 7 8 9 VGS (V) GADG200720180953RID 0.185 VGS = 10 V 0.180 2 100 0.165 0 Qg (nC) 0.160 0 16 6 0.190 200 12 5 0.195 4 8 4 RDS(on) (Ω) 300 4 3 Figure 6. Static drain-source on-resistance 6 0 0 DS12706 - Rev 1 400 0 2 20 24 0.175 0.170 2 4 6 8 10 12 14 ID (A) page 5/15 STL24N60M6 Electrical characteristics (curves) Figure 7. Capacitance variations C (pF) Figure 8. Output capacitance stored energy EOSS (µJ) 10 GADG190720181455CVR GADG190720181457EOS 9 10 3 CISS 8 7 6 10 2 5 COSS 10 1 10 0 10 -1 f = 1 MHz CRSS 10 0 10 1 10 2 VDS (V) Figure 9. Normalized gate threshold voltage vs temperature VGS(th) (norm.) GADG190720181456VTH 2 1 0 0 100 200 300 400 500 600 VDS (V) Figure 10. Normalized on-resistance vs temperature RDS(on) (norm.) GADG190720181456RON VGS = 10 V 1.8 1.0 1.4 0.9 1 0.8 0.6 0.7 0.6 -75 3 2.2 ID = 250 µA 1.1 4 -25 25 75 125 Tj (°C) Figure 11. Normalized V(BR)DSS vs temperature V(BR)DSS (norm.) GADG190720181457BDV -25 25 75 125 Tj (°C) Figure 12. Source-drain diode forward characteristics VSD (V) GADG190720181457SDF 1.1 ID = 1 mA 1.08 0.2 -75 Tj = -50 °C 1.0 1.04 0.9 Tj = 25 °C 1.00 0.8 0.96 0.92 0.88 -75 DS12706 - Rev 1 Tj = 150 °C 0.7 0.6 -25 25 75 125 Tj (°C) 0.5 0 2 4 6 8 10 12 14 ISD (A) page 6/15 STL24N60M6 Test circuits 3 Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Test circuit for gate charge behavior VDD RL RL + VD VGS 3.3 µF 2200 µF VDD IG= CONST VGS RG + pulse width D.U.T. 2200 μF PW D.U.T. 100 Ω 2.7 kΩ VG 47 kΩ GND1 (driver signal) GND2 (power) 1 kΩ GND1 AM15855v1 GND2 GADG180720181011SA Figure 15. Test circuit for inductive load switching and diode recovery times A A D.U.T. FAST DIODE Figure 16. Unclamped inductive load test circuit A L D G S L=100µH B B D 25Ω VD 3.3 µF B + 1000 µF 2200 µF 3.3 µF + VDD VDD ID G S RG D.U.T. Vi D.U.T. Pw GND2 GND1 GND1 GND2 AM15858v1 AM15857v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12706 - Rev 1 page 7/15 STL24N60M6 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS12706 - Rev 1 page 8/15 STL24N60M6 PowerFLAT™ 8x8 HV package information 4.1 PowerFLAT™ 8x8 HV package information Figure 19. PowerFLAT™ 8x8 HV package outline 8222871_Rev_4 DS12706 - Rev 1 page 9/15 STL24N60M6 PowerFLAT™ 8x8 HV package information Table 8. PowerFLAT™ 8x8 HV mechanical data Ref. Dimensions (in mm) Min. Typ. Max. A 0.75 0.85 0.95 A1 0.00 A3 0.10 0.20 0.30 b 0.90 1.00 1.10 D 7.90 8.00 8.10 E 7.90 8.00 8.10 D2 7.10 7.20 7.30 E1 2.65 2.75 2.85 E2 4.25 4.35 4.45 e L 0.05 2.00 BSC 0.40 0.50 0.60 Figure 20. PowerFLAT™ 8x8 HV footprint 8222871_REV_4_footprint Note: DS12706 - Rev 1 All dimensions are in millimeters. page 10/15 STL24N60M6 PowerFLAT™ 8x8 HV packing information 4.2 PowerFLAT™ 8x8 HV packing information Figure 21. PowerFLAT™ 8x8 HV tape P2 (2.0±0.1) T (0.30±0.05) P0 (4.0±0.1) D0 ( 1.55±0.05) D1 ( 1.5 Min) P1 (12.00±0.1) W (16.00±0.3) F (7.50±0.1) B0 (8.30±0.1) E (1.75±0.1) A0 (8.30±0.1) K0 (1.10±0.1) Note: Base and Bulk qu antity 3000 pcs 8229819_Tape_revA Note: All dimensions are in millimeters. Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape DS12706 - Rev 1 page 11/15 STL24N60M6 PowerFLAT™ 8x8 HV packing information Figure 23. PowerFLAT™ 8x8 HV reel 8229819_Reel_revA Note: DS12706 - Rev 1 All dimensions are in millimeters. page 12/15 STL24N60M6 Revision history Table 9. Document revision history DS12706 - Rev 1 Date Version 06-Aug-2018 1 Changes Initial release. page 13/15 STL24N60M6 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 PowerFLAT™ 8x8 HV package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DS12706 - Rev 1 page 14/15 STL24N60M6 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12706 - Rev 1 page 15/15